A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits

Abstract

We present a comprehensive comparative analysis of FinFET and Trigate device characteristics, 6T SRAM stability and logic circuits. The impact of intrinsic random device variations, including fin Line Edge Roughness (LER), Work Function Variation (WFV) and fin width scaling on FinFET and Trigate device Subthreshold Slope (S.S.), V T , 6T SRAM Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) are investigated and compared by using 3D atomistic TCAD simulation. The results indicate that Trigate device shows slightly better variability control under the same electrical width and fin width (10nm and 7nm) considering fin LER and WFV. Next, we investigate the impact of single charged trap induced Random Telegraph Noise (RTN) on FinFET and Trigate device characteristics, 6T SRAM and logic circuits. The top-gate and the lower fin height of Trigate device under the same electrical width and fin width cause the current density to concentrate close to the bottom of the fin, resulting in stronger dependence on the location of the trap, larger RTN ΔI D /I D amplitude and larger ΔV T with a trap placed at the worst position under fin LER and WFV. The impact of RTN trapping/detrapping on 6T SRAM RSNM, the leakage-delay of inverter, Two-Way NAND and 2-To-1 Multiplexer (MUX) are examined. With degreasing supply voltage, the RTN degradation of Trigate SRAM RSNM and logic circuits become larger compared with the FinFET counterparts.