NAND Flash Memory Application Research Articles

Exploring Disturb Characteristics in 2D and 3D Ferroelectric NAND Memory Arrays for Next-Generation Memory Technology.

Ferroelectric transistors are considered promising for next-generation 3D NAND technology due to their lower power consumption and faster operation compared to conventional charge-trap flash memories. However, ensuring their suitability for such applications requires a thorough investigation of array-scale reliability. This study specifically examines the suitability of hafnia-based ferroelectric transistors for advanced 3D NAND applications, with a specific focus on establishing a disturb-free voltage scheme to ensure the reliability of ferroelectric transistors within the array. Our key finding highlights the crucial role of optimal pass voltage in achieving disturb-free operation in both 2D and 3D ferroelectric NAND arrays. Additionally, the study indicates that read disturb remains negligible when an appropriate read voltage is applied. These insights provide a practical strategy for achieving reliable operation in 2D and 3D ferroelectric NAND, highlighting the potential of hafnia-based ferroelectric materials to meet the evolving requirements of high-density and reliable NAND flash memory applications.

An Optimized Device Structure with a Highly Stable Process Using Ferroelectric Memory in 3D NAND Flash Memory Applications

In this paper, we propose an optimized device structure with a highly stable process that addresses threshold voltage shift issues in the String-Select-Line (SSL) and Ground-Select-Line (GSL) gates using ferroelectric memory in 3D NAND flash memory applications. The proposed device utilizes nickel (Ni) instead of tungsten (W) for the GSL and SSL gates, enabling optimized polarization properties during the annealing process and leveraging the disparity in thermal expansion coefficients. Notably, the difference in thermal expansion coefficient from tungsten (W), employed in other Word Line (WL) gates, allows effective control over polarization properties. To validate the proposed structure, we fabricated and measured a Metal–Ferroelectric–Insulator–Silicon (MFIS) capacitor utilizing Hafnium–Zirconium Oxide (HZO) material. The measurement results indicate that a change in the upper metal layer results in a more than fivefold increase in the variance of polarization characteristics between the WL gates (responsible for the memory function) and the SSL and GSL gates dedicated to channel control. In addition, process simulation was conducted using the same device structure, confirming the application of tensile stress to the HZO thin film in the case of a W electrode and compressive stress in the case of a Ni electrode. Furthermore, applying this controlled polarization characteristic parameter to the 3D NAND flash memory structure revealed a reduction in the threshold voltage shift of the control gate from a previous change of 2.6 V or more to 0.05 V, facilitating stable control.

High Mobility and GIDL Erase-Compatible Characteristics in Hybrid Channel (Poly-Si/IGO) for Ultrahigh 3D NAND Flash Memory Applications

High Mobility and GIDL Erase-Compatible Characteristics in Hybrid Channel (Poly-Si/IGO) for Ultrahigh 3D NAND Flash Memory Applications

Optimization of Bump Defect at High-Concentration In-Situ Phosphorus Doped Polysilicon/TEOS Oxide Interface for 3D NAND Flash Memory Application

In the 3D NAND Flash memory manufacturing process, high-concentration in-situ phosphorus-doped polysilicon and TEOS oxide stack will produce bump defects at the interfaces, causing pattern defects and electrical failures. The formation mechanism of bump defects caused by oxygen-containing groups and phosphorus at the lower and upper interfaces of phosphorus-doped polysilicon is investigated in detail. Two methods were demonstrated to reduce bump defects, wet processing and Rapid Thermal Oxidation (RTO). The wet processing is to remove oxygen-containing groups and phosphorus, while the RTO process increases the solubility of phosphorus in silicon. Both methods have significantly reduced bump defects and greatly increased the yield rate, and further verify the proposed formation mechanism of bump defects.

Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages

Recently, symmetric block-wise concatenated-BCH (SBC-BCH) codes are proposed as strong error-correcting codes (ECCs) based on hard-decision channel outputs, which is especially suited for storages using NAND flash memories. Targeting energy-efficient NAND flash memory applications, this paper presents an energy-optimized decoder architecture which includes an iterative decoder for a SBC-BCH code as a main decoder and a low-complexity auxiliary decoder for a block-wise single parity-check (BSPC) code. The auxiliary decoder is opportunistically in action to break the dominant error bound associated with the SBC-BCH code, which allows one to lower the uncorrectable bit-error-rate (UBER) to 10−15 in an energy efficient way. This work presents several design-level optimizations for further enhancing the energy-efficiency of the iterative SBC-BCH decoder. More precisely, the new initialization scheme is proposed for ensuring the energy-efficient seamless decoding scenario. The syndrome tracking is applied to eliminate the previous syndrome calculation and the reordered Chien search further enhances the energy-efficiency as well as the decoding throughput. Targeting a 0.9-rate 4KB SBC-BCH code for commercialized storages using NAND flash memories, a prototype decoder consisting of both the iterative main and auxiliary decoders is designed in a 65-nm CMOS process. By applying the proposed optimizations, the prototype decoder achieves an energy-efficiency of 3.43 pJ/b while providing a decoding throughput of 13.2 Gb/s, which is superior to the previous state-of-the-art decoders for mobile storages.

Comparison With Nitride Interface Defects and Nanocrystals for Charge Trapping Layer Nanowire Gate-All-Around Nonvolatile Memory Performance

This paper demonstrates novel silicon–oxide–nitride–nitride–oxide–silicon (SONNOS) and silicon-oxide-nanocrystals-oxide-silicon (SOncOS) nonvolatile memory (NVM) that is based on nanowires gate-all-around (GAA) structure. SONNOS and SOncOS NVM exploit doubly stacked Si3N4 (NN) interface defects and silicon nanocrystals as charge trapping layers, respectively. Experimental results reveal that SONNOS NVM has superior memory characteristics than SOncOS NVM. With respect to memory reliability, the SONNOS NVM retains 86% memory window after 104 program/erase cycles, and the memory window retains 42% of the originally stored charge after ten years. Such doubly stacked Si3N4 layers provide additionally charge trapping sites in CTL, improving the memory performance of NVM. In the future, SONNOS GAA NVMs will be easily integrated in 3-D nand flash memory applications.

Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage

For highly scalable NAND flash memory applications, a compact (4F2/cell) nonvolatile memory architecture is proposed and investigated via threedimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

Self-aligned double-patterning layout decomposition for two-dimensional random metals for sub-10-nm node design

Self-aligned double patterning (SADP) is popularly in production use for one-dimensional-type dense patterns with good pitch control in NAND Flash memory applications and the fin layer patterning of FinFET devices, but it is still challenging to apply SADP to two-dimensional (2-D) random metal patterns. We describe the SADP layout decomposition methods for complex 2-D layouts. The SADP for complex logic metals consists of a two mask approach using a core (mandrel) mask and a trim mask. This paper describes methods for automatically choosing and optimizing the manufacturability of base core mask patterns, generating assist core patterns, and optimizing trim mask patterns to accomplish high quality layout decomposition in the SADP process. Our technique is validated with 22-nm node industrial standard cells and logic designs, which can be applicable to sub-10-nm node design. Experimental results show that our proposed layout decomposition for SADP effectively decomposes many challenging 2-D layouts.

High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives

This paper presents a high-throughput and low-complexity BCH decoder for NAND flash memory applications, which is developed to achieve a high data rate demanded in the recent serial interface standards. To reduce the decoding latency, a data sequence read from a flash memory channel is re-encoded by using the encoder that is idle at that time. In addition, several optimizing methods are proposed to relax the hardware complexity of a massive-parallel BCH decoder and increase the operating frequency. In a 130-nm CMOS process, a (8640, 8192, 32) BCH decoder designed as a prototype provides a decoding throughput of 6.4 Gb/s while occupying an area of 0.85 mm2.

Stacked-nanowire device with virtual source/drain (SD-VSD) for 3D NAND flash memory application

A new stacked-nanowire device is proposed for 3-dimensional (3D) NAND flash memory application. Two single-crystalline Si nanowires are stacked in vertical direction using epitaxially grown SiGe/Si/SiGe/Si/SiGe layers on a Si substrate. Damascene gate process is adopted to make the gate-all-around (GAA) cell structure. Next to the gate, side-gate is made and device characteristics are controlled by the side-gate operations. By forming the virtual source/drain using the fringing field from the side-gate, short channel effect is effectively suppressed. Array design is also investigated for 3D NAND flash memory application.

Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory

In this paper, a 3-D nand Flash memory array having multiple single-crystal Si nanowires is investigated. Device structure and fabrication process are described including the electrical isolation of stacked nanowires. Numerical simulation results focused on nand Flash memory operation are delivered. Devices and array with stacked bit lines are fabricated, and memory characteristics such as program/erase select gate operation are measured. Array scheme is also discussed for the high-density bit-cost scalable 3-D stacked bit-line nand Flash memory application.

Modified Potential Well Formed by $\hbox{Si/SiO}_{2}/ \hbox{TiN/TiO}_{2}/\hbox{SiO}_{2}/\hbox{TaN}$ for Flash Memory Application

This paper proposes a modified engineered-potentialwell (MW) for NAND flash memory application. The MW was formed by using a transitional SiO2/SiOx,Na-TiOx,Ny tunnel barrier, a trap-rich TiO2 trapping layer, and an abrupt SiO2 block barrier. The transitional tunnel barrier shrinks to enhance the tunneling of carriers during programming/erasing (P/E) and extends to suppress charge loss during data retention. Deep-level transient spectroscopy suggests that this tunnel barrier has few shallow traps after a N2 + O2 thermal treatment, and the TiO2 trapping layer has deep electron traps. With the variable tunnel barrier and deep electron traps, the MW device showed promising performance in fast programming ( 106 P/E cycles), large threshold voltage window (ΔVth =M> V), as well as improved data retention at 125 °C.

Fabrication and characterization of sub-0.6-µm ferroelectric-gate field-effect transistors

Sub-micron-gate Pt/SrBi2Ta2O9/Hf-Al-O/Si ferroelectric-gate field-effect transistors (FeFETs) were successfully fabricated using electron-beam lithography, metal hard mask technique and dry etching. Scanning electron microscopy measurements revealed that the gate length of a fabricated FeFET was 0.56 µm. Drain current versus gate voltage curves showed steep switching and a memory window of 0.93 V when the applied gate voltage range was 1 ± 5 V. Excellent endurance characteristics were observed up to 108 program/erase cycles, indicating that the FeFETs are suitable for use in NAND flash memory applications. Retention measurements showed that the drain current ON/OFF ratio (104) did not undergo any significant change up to 105 s.

3D NAND flash memory with laterally-recessed channel (LRC) and connection gate architecture

A three-dimensional (3D) stacked bit-line NAND flash memory is investigated. The fabrication process flow for the formation of a laterally-recessed bit-line stack is described. Program operation is simulated using a stacked bit-line structure. Inter-layer interference (ILI) is addressed and the minimum isolation oxide thickness between stacked bit-lines is extracted. Simple device and array with the laterally-recessed bit-line stack are fabricated and electrical characteristics are measured. A new array architecture having a connection gate is designed for the 3D stacked bit-line NAND flash memory application.

Data retention characteristics of MANOS-type flash memory device with different metal gates at various levels of charge injection

We investigated the impact of charge injection and metal gates (Al and Pt) on the data retention characteristics of metal–alumina–nitride–oxide–silicon (MANOS) devices for NAND flash memory application. Through the theoretical and experimental results, the highly injected charge (Δ V TH) could cause the band bending of Al 2O 3, which reduced the tunneling distance across Al 2O 3. Thus, the dominant charge loss path is not only toward SiO 2 but also toward Al 2O 3 direction. Compared to low-metal work function ( Ф M), ONA stack with high- Ф M showed better data retention characteristics, even if Δ V TH is high. This could be explained by Fermi level alignment for different Ф M, which results in the reduction of electric field across the Al 2O 3 compensated by the Δ Ф M ( Ф Pt − Ф Al).

Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure

A new SONOS flash memory device with recess channel and side-gate was proposed and designed in terms of recess depth, doping profile, and side-gate length for sub-40nm flash memory technology. The key features of the devices were characterized through 3-dimensional device simulation. This cell structure can store 2 or more bits of data in a cell when it is applied to NOR flash memory. It was shown that channel doping profile is very important depending on NOR or NAND applications. In NOR flash memory application, the localized channel doping under the source/drain junction is very important in designing threshold voltage (Vth) and suppression of drain induced barrier lowering (DIBL). In our work, this cell structure is studied not only for NAND flash memory application but also for NOR flash application. The device design was performed in terms of electrical characteristics (Vth, DIBL and SS) by considering device structure and doping profile of the cell.

Material properties of anisotropic conductive films (ACFs) and their flip chip assembly reliability in NAND flash memory applications

In this paper, the material properties of anisotropic conductive films (ACFs) and ACF flip chip assembly reliability for a NAND flash memory application were investigated. Measurements were taken on the curing behaviors, the coefficient of thermal expansion (CTE), the modulus, the glass transition temperature ( T g), and the die adhesion strength of six types of ACF. Furthermore, the bonding processes of the ACFs were optimized. After the ACF flip chip assemblies were fabricated with optimized bonding processes, reliability tests were then carried out. In the pressure cooker test, the ACF with the highest adhesion strength showed the best reliability and the ACF flip chip assembly revealed no delamination at the chip-ACF interface, even after 96 h. In the high temperature storage test and the thermal cycling test, the reliability of the ACF flip chip assembly strongly depends on the T g value of the ACF. In the thermal cycling test, in particular, which gives ACF flip chip assemblies repetitive shear stress, high value of CTE above T g accelerates the failure rate of the ACF flip chip assembly. From the reliability test results, ACFs with a high T g and a low CTE are preferable for enhancing the thermal and thermo-mechanical reliability. In addition, a new double-sided chip package with a thickness of 570 μm was demonstrated for NAND flash memory application. In conclusion, this study verifies the ACF feasibility, and recommends the optimum ACF material properties, for NAND flash memory application.

Hybrid nanocrystal FinFET with large P∕E window for MLC NAND Flash memory application

The engineered trap layer with nanocrystal and high-k blocking oxide are applied to the FinFET structure. The increased trap density of the hybrid nanocrystal trap layer and the enhanced leakage reduction of Al x O y are proposed as a dominant role of the larger program and erase window of 8.3 V which is applicable to the MLC Flash memory device