Optimization of Bump Defect at High-Concentration In-Situ Phosphorus Doped Polysilicon/TEOS Oxide Interface for 3D NAND Flash Memory Application

Dongxue Zhao,Dongyu Fan,Zongliang Huo,Wenxi Zhou,Zhiliang Xia,Yuancheng Yang,Linchun Wu,Tao Yang,Lei Liu

doi:10.1109/jeds.2021.3123844

Dongxue Zhao, Dongyu Fan + Show 7 more

Open Access

https://doi.org/10.1109/jeds.2021.3123844

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Abstract

In the 3D NAND Flash memory manufacturing process, high-concentration in-situ phosphorus-doped polysilicon and TEOS oxide stack will produce bump defects at the interfaces, causing pattern defects and electrical failures. The formation mechanism of bump defects caused by oxygen-containing groups and phosphorus at the lower and upper interfaces of phosphorus-doped polysilicon is investigated in detail. Two methods were demonstrated to reduce bump defects, wet processing and Rapid Thermal Oxidation (RTO). The wet processing is to remove oxygen-containing groups and phosphorus, while the RTO process increases the solubility of phosphorus in silicon. Both methods have significantly reduced bump defects and greatly increased the yield rate, and further verify the proposed formation mechanism of bump defects.

Highlights

WITH the development of big data and artificial intelligence technology, 3D NAND flash memory, as a kind of large-capacity memory, has higher requirements for storage capacity
The number of layers of 3D NAND flash memory is increasing by the year
A layer of 300nm TEOS oxide is deposited on the substrate, and a layer of 400nm high-concentration in-situ phosphorus-doped amorphous silicon is grown with PH3 and SiH4 at a temperature of >500oC

Summary

Introduction

WITH the development of big data and artificial intelligence technology, 3D NAND flash memory, as a kind of large-capacity memory, has higher requirements for storage capacity. The number of layers of 3D NAND flash memory is increasing by the year. To significantly increase the storage density, XY dimension shrinking becomes another key critical scaling direction. The conventional architecture is the peripheral circuit nearby the array cell (PNC), the peripheral circuit under the array cell (PUC) and the peripheral circuits above the array cell (Xtacking) are more advanced with higher storage density. Zhou are with the Yangtze Memory Technologies Co., Ltd., Wuhan 430205, China

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