N-type MOS Transistors Research Articles

Trap Recovery by in-Situ Annealing in Fully-Depleted MOSFET With Active Silicide Resistor

This work reports first original results on the impact of active in-situ electro-thermal recovery, on the electrical and low-frequency noise characteristics of N-type MOS transistor with thick high-k metal gate oxide, from 28 nm Fully Depleted Silicon-On-Insulator (FDSOI) process. In order to recover “typical” device characteristics, four cycles of local thermal annealing up to 590K are applied for 14 ms each, using an active silicide source. Experimental results reveal an important improvement of the “corner” transistor’s I-V behavior allowing the recovery of “typical” device characteristics. An increase of the maximum transconductance by 43% is obtained. In the same time, a typical device stays unaffected by this local annealing. Low-frequency noisemeasurements showa clear reduction of the 1/f noise and Random Telegraph Noise by almost one decade, after the electro-thermal recovery. This can explain the improvement of the electrical characteristics by annealing of defects.

Open-circuit voltage photodetector architecture for infrared imagers

We theoretically and experimentally investigate the application of an open-circuit voltage photodetector (VocP) architecture for mid-wave infrared (MWIR, 3–5 μm) detection and imaging. In contrast to conventional reverse-bias (RB) operation of the diode, which generates a photocurrent that is proportional to the photon irradiance, we evaluate the potential of using unbiased diodes that generate an open-circuit voltage, VOC, under illumination. The predicted Noise Equivalent Differential Temperature (NEDT) of a VocP is inferior to conventional RB when we assume an infinite well capacity and fixed integration time, but the prediction reverses when the actual well capacity of a readout integrated circuit (ROIC) is taken into account. Therefore, for a focal plane array (FPA) with a ROIC, we predict superior NEDT for the VocP. To demonstrate this concept, we fabricated and tested a basic VocP unit-cell architecture by connecting the VOC anode of a MWIR photodiode to the gate of an n-type metal-oxide semiconductor transistor that is operated in sub-threshold. Very good agreement is obtained between the analytical model and the observed drain current of the transistor over three orders of photon irradiance (1015–1018 photons/sec-cm2). The decoupling of the diode photocurrent from the integration capacitor in the circuit leads to a lower dark current that allows for longer integration times and improved sensitivity. This potentially can have a great impact on the performance and functionality of FPAs, leading to FPAs with better NEDT at a higher operating temperature, wider dynamic range, and smaller pixel size leading to larger array formats.

On-Chip Over-Voltage Protection Design Against Surge Events on the CC Pin of USB Type-C Interface

As fast charging being a comprehensive application in universal serial bus (USB) type-C products, the high-power delivery may cause the USB type-C interface in the high risk of surge events. Therefore, a switch realized by high voltage N-type metal oxide semiconductor-transistor (HVNMOS) has been added to the configuration channel (CC) pin to prevent the internal circuits from surge damage. However, hot carrier degradation (HCD) on the HVNMOS was induced by surge events, especially when the HVNMOS was operating in the ON-state. To mitigate HCD on the HVNMOS switch during surge events, a new over-voltage protection (OVP) design with selected voltage-level detection was proposed and verified in a 0.15-μm BCD technology. The proposed OVP circuit with a positive feedback is designed to turn off the gate of the HVNMOS switch for a longer time when surge zapping on the CC pin. The experimental results from silicon chip have successfully verified the proposed OVP structure in device level and circuit level, respectively.

A Regulated Temperature-Insensitive High-Voltage Charge Pump in Standard CMOS Process for Micromachined Gyroscopes.

Micromachined gyroscopes require high voltage (HV) for actuation and detection to improve its precision, but the deviation of the HV caused by temperature fluctuations will degrade the sensor’s performance. In this paper, a high-voltage temperature-insensitive charge pump is proposed. Without adopting BCD (bipolar-CMOS-DMOS) technology, the output voltage can be boosted over the breakdown voltage of n-well/substrate diode using triple-well NMOS (n-type metal-oxide-semiconductor) transistors. By controlling the pumping clock’s amplitude continuously, closed-loop regulation is realized to reduce the output voltage’s sensitivity to temperature changes. Besides, the output level is programmable linearly in a large range by changing the reference voltage. The whole circuit has been fabricated in a 0.18-m standard CMOS (complementary metal-oxide-semiconductor) process with a total area of 2.53 mm. Measurements indicate that its output voltage has a linear adjustable range from around 13 V to 16.95 V, and temperature tests show that the maximum variations of the output voltage at are less than 1.1%.

Modelling and kink correction of bulk CMOS at liquid helium temperature

Cryogenic characterisation and modelling of 0.18 μm CMOS technology (1.8 and 5 V) is presented in this Letter. Several P-type MOS and N-type MOS transistors with different width to length ratios were extensively characterised under various bias conditions at temperatures ranging from 300 K down to 4.2 K. The authors extracted their fundamental physical parameters and developed a compact model based on BSIM3V3. A simple subcircuit was built to correct the kink effect. The RMS error of test results and modelling results is <;3%.

Charge Pumping Under Spin Resonance in Si(100) Metal-Oxide-Semiconductor Transistors

Gate-pulse-induced recombination, known as the charge pumping (CP), is a fundamental carrier recombination process, and has been utilized as a method for analyzing electrical properties of defects (or dangling bonds) at the transistor interfaces, which is now recognized to be well-matured and conventional. Nevertheless, neither the origin (the bonding configuration) of the defects responsible for the CP, nor their detailed recombination sequence has been clarified yet for Si metal-oxide-semiconductor (MOS) interfaces. In order to address these problems, we investigated the CP under spin resonance conditions at temperatures ranging from 27 to 300 K in Si(100) n-type MOS transistors. We obtained evidence that Pb0 and E' centers, the two major dangling bonds at (and near) the Si(100) interface, participate in the CP recombination process. We also show that the spin-dependent CP process is explained by the formation of electron-electron spin pairs, which in turn reveals that the CP via Pb0 and E' centers is inherently a two-electron process.

Investigation of characteristics and hot-carrier reliability of high-voltage MOS transistors with various doping concentrations in the drift region

The effect of doping concentration in the n− drift region on the characteristics and hot-carrier reliability in high-voltage n-type MOS transistors is investigated. Results show that a proper increase in the n− drift doping concentration improves device characteristics. In addition, a proper increase in the n− drift doping concentration reduces hot-carrier induced device degradation. Technology computer-aided design simulation results suggest that the impact of hot-carrier induced interface charge generation on device degradation is alleviated for a higher n− drift doping concentration. Such a result can explain the reduction in hot-carrier induced device degradation for the device with a higher doping concentration in the n− drift region.

Effect of Oxide Thickness Variation in Sub-micron NMOS Transistor

Aggressive scaling of metal oxide semiconductor (MOS) devices have resulted in the use of ultrathin gate oxides, which in turn enhanced the device performance. This work examines different components of tunnelling electron in scaled n-type MOS (NMOS) with ultrathin gate oxides (1.2-2.0 nm). Direct tunnelling currents are focused on the currents between the gate and the channel region in the substrates. The gate direct tunnelling currents are investigated by theoretical modelling and simulation experiments and their effects on the leakage current from those two approaches are compared. The simulation of this project was carried out using Sentaurus TCAD software. A 90 nm NMOS transistor is simulated to investigate the electron tunnelling phenomenon and its effect on the device performance. The 90 nm NMOS device was designed and characterized using Sentaurus TCAD software. In this project, there are two major simulations done using Sentaurus Process and Sentaurus Device. There are four parameters being investigated, which are is oxide thickness (Tox), threshold voltage (VTH), drain voltage (VD) and gate voltage (VG), to obtained result of drain current (ID) and leakage current (IOFF). The simulations data results are listed in the Inspect tools and used to plot graphs to compare between simulation and calculation results. The electrons start tunnelling at the Tox of 1.4 nm with resulting in large IOFF of 2.45×10-9A at VD of 0.5V. The simulation results are found to be almost identical with the theoretical modelling.

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Abnormal Recovery Phenomenon Induced by Hole Injection During Hot Carrier Degradation in SOI n-MOSFETs

This letter investigates an abnormal recovery phenomenon induced by hole injection during hot carrier degradation in silicon-on-insulator n-type metal–oxide–semiconductor transistors. The method by which the hole injection induces the abnormal recovery behavior can be clarified by different hot carrier degradation (HCD) measurement sequences. According to this HCD result, the channel surface energy band is drawn down and the interface defect will be temporarily shielded, an effect caused by the trapped hole. Furthermore, results of different stress voltage experiments indicate that the amount of hole injection is determined by the electric field between the gate and drain.

Reduction of NEP variations for terahertz detectors using Schottky barrier diodes in CMOS

Variations of low-frequency noise including flicker and Lorentzian spectra are the dominant source of variation of noise equivalent power (NEP) for terahertz detectors using diode-connected N-type MOS (NMOS) transistors. The low-frequency noise of Schottky diodes fabricated in the same CMOS process as the NMOS detectors are dominated by generation and recombination noise. At 1 MHz modulation frequency, the noise of Schottky barrier diodes (SBDs) and its variation are ∼2× lower than those of diode-connected NMOS transistors. It should be possible to reduce the variation of NEP by ∼2× using Schottky diode detectors modulated at 1 MHz.

An accurate model for predicting high frequency noise of nanoscale NMOS SOI transistors

A nonlinear and scalable model suitable for predicting high frequency noise of N-type Metal Oxide Semiconductor (NMOS) transistors is presented. The model is developed for a commercial 45nm CMOS SOI technology and its accuracy is validated through comparison with measured performance of a microwave low noise amplifier. The model employs the virtual source nonlinear core and adds parasitic elements to accurately simulate the RF behavior of multi-finger NMOS transistors up to 40GHz. For the first time, the traditional long-channel thermal noise model is supplemented with an injection noise model to accurately represent the noise behavior of these short-channel transistors up to 26GHz. The developed model is simple and easy to extract, yet very accurate.

Analysis of high-voltage metal–oxide–semiconductor transistors with gradual junction in the drift region

The device characteristics and hot-carrier-induced degradation of high-voltage n-type metal–oxide–semiconductor transistors with traditional and gradual junctions in the drift region are studied in this work. The gradual junction used in this study is realized by self-aligned N− implantation through dual thicknesses of screen oxide during N− drift implantation. Compared with traditional devices, devices with gradual junctions have improved off-state breakdown voltage (VBD) without sacrificing on-state driving current and hot-carrier-induced degradation. More improvement in VBD is observed if the dimensions of the device are larger. The mechanism responsible for VBD improvement in devices with gradual junctions is also investigated by using technology computer-aided-design simulations.

Single DV-DXCCII Based Voltage Controlled First Order All-pass Filter with Inverting and Non-inverting responses

In this paper, a new voltage controlled first order all-pass filter is presented. The proposed circuit employs a single Differential Voltage Dual-X second generation Current Conveyor (DV-DXCCII), a NMOS (n-type Metal Oxide Semiconductor) transistor operated in the triode region as an active resistor and a grounded capacitor. The proposed all-pass filter provides both inverting and non inverting voltage-mode outputs simultaneously from the same configuration without any matching constraint. Non-ideal analysis along with sensitivity analysis is investigated. The proposed circuit has low active and passive sensitivities. The Monte Carlo analysis is also done for showing good sensitivity performances of the proposed circuit. In addition, to utilize the feature of cascadability, an application of higher order filter is also given. Moreover, the use of grounded capacitor makes the proposed circuit particularly attractive for Integrated Circuit (IC) implementation point of view. The theoretical results are validated through PSPICE simulations with TSMC 0.18 μm Complementary Metal Oxide Semiconductor (CMOS) process parameters.

Drift region doping effects on characteristics and reliability of high-voltage n-type metal–oxide–semiconductor transistors

In this study, off-state breakdown voltage (VBD) and hot-carrier-induced degradation in high-voltage n-type metal–oxide–semiconductor transistors with various BF2 implantation doses in the n− drift region are investigated. Results show that a higher BF2 implantation dose results in a higher VBD but leads to a greater hot-carrier-induced device degradation. Experimental data and technology computer-aided design simulations suggest that the higher VBD is due to the suppression of gate-induced drain current. On the other hand, the greater hot-carrier-induced device degradation can be explained by a lower net donor concentration and a different current-flow path, which is closer to the Si–SiO2 interface.

2.4 GHz CMOS self‐biased power amplifier with embedded diode lineariser

A high-linearity CMOS power amplifier (PA) operating at 2.4 GHz with an integrated diode lineariser is presented. A diode-connected N-type MOS transistor is used to increase the V gs of the power transistor as input power increases for linearity improvement. The CMOS PA fabricated in 180 nm CMOS technology achieved 32 dB small signal gain, 30.2 dBm P sat, 28.2 dBm P 1 dB, and a 31.1% peak power added efficiency. By adopting the proposed diode lineariser, the output 1 dB is improved from 24.9 to 28.2 dBm.

Low start‐up voltage dc–dc converter with negative voltage control for thermoelectric energy harvesting

This Letter presents a low start-up voltage dc–dc converter for low-power thermoelectric systems which uses a native n-type MOS transistor as the start-up switch. The start-up voltage of the proposed converter is 300 mV and the converter does not need batteries to start up. The negative voltage control is proposed to reduce the leakage current caused by native n-type transistor and increase the efficiency. The proposed converter was designed using standard 0.18 µm CMOS process with chip size of 0.388 mm2. The peak efficiency is 63% at load current of 1.5 mA. The proposed converter provides output voltage >1 V at maximum load current of 3.2 mA.

RF characteristics of 0.13-μm NMOS transistors for millimeter-wave application

Purpose – The purpose of this paper is to present the high-frequency performance of 0.13-μm n-type metal-oxide-semiconductor (NMOS) transistors with various multi-finger configurations for implementation in millimeter-wave (mm-wave) frequency. Design/methodology/approach – A folded-like double-gate transistor layout is designed to enable the transistor to work in the mm-wave region. Different sizes of transistors with variation in finger width (WF ) and number of fingers (NF ) were fabricated to determine the optimum size of the transistor. The extrinsic parasitic elements of selected transistors were extracted and investigated. The radio frequency (RF) performance of these samples were then analyzed and compared. Findings – The proposed layout performed well with the highest maximum oscillation frequency (fmax ) achieved at 122 GHz. Based on the comparison done, the optimum WF obtained for the layout is at 2.0 μm. It is found that the extrinsic parasitic capacitance is more dominant than the parasitic resistance in affecting the fmax . In s-parameter analysis, it is observed that the transistor with the least NF has smaller variance in small-signal gain throughout the measurement frequency. The maximum stable gain for the samples is also found to be roughly similar and independent of NF . Originality/value – A new layout structure for an NMOS transistor that works in mm-wave frequency is proposed. Experimental analyses presented here cover for both NF and WF , unlike others which focus on either NF or WF only.

Influence of Frequency Dependent Time to Breakdown on High-K/Metal Gate Reliability

Time-dependent dielectric breakdown and stress-induced leakage current (SILC) behavior of a 28-nm hafnium-based high-k/metal gate n-type MOS transistors are investigated under dc and ac conditions. Compared with the constant voltage stress results under dc conditions, a decrease in device lifetime is observed for low-frequency ac stress. Degradation enhancement and SILC behavior are attributed to defect generation in the SiO2 interface layer. For high-frequency ac stress, a lifetime improvement is observed, because of reduced trap generation.

The electrical and structural properties of HfO2/SrTiO3 stacked gate dielectric with TiN metal gate electrode

The electrical and structural properties of HfO2/SrTiO3 composite gate dielectric are discussed for achieving higher dielectric constant to reduce equivalent oxide thickness (EOT) as well as to tune threshold voltage (VTH) in n-type metal oxide semiconductor transistor. Compared to atomic layer deposited (ALD) HfO2 alone, adding 0.5–1.0nm sputtered SrTiO3 layer into ALD HfO2 gate dielectric attains EOT scaling down to about 0.6nm, ~700mV negative VTH shift, comparable gate leakage current at both fixed 1V and VTH+0.8V overdrive conditions and electron mobility with of 137cm2/V.s at 0.6nm EOT. This is attributed to the significant modification of the interfacial layer (IL), resulting from Sr diffusion into sub-SiOx IL during subsequent anneal in gate-first transistor processes. It leads to SrOx IL formation between high-k gate insulator layer and Si substrate, where its dielectric constant is about three times higher than that of SiOx IL.