NMOS Capacitors Research Articles

Comparative study of mechanical stress-induced flat-band voltage change in MOS capacitor and threshold voltage change in MOSFET fabricated on 4H-SiC (0001)

The impact of mechanical uniaxial stress on electrical characteristics of 4H-SiC (0001) n-type MOSFET (n-MOSFET) was systematically investigated by a mechanical 4-point bending method. Expected variation of field-effect mobility with stress was observed and for the first time, a direct relationship between uniaxial stress and significant change in threshold voltage (V th) on lateral SiC MOSFET was investigated systematically. The observed change of V th was as large as 40 mV with a stress of 170 MPa. By comparing with flat-band voltage (V fb), it was concluded that a change in V th mainly consists of change in V fb on n-MOS capacitor with mechanical stress. Even though the possible origins of such V fb change with stress are not clarified yet, they were suggested to be either the change in band alignment or the change in fixed charge density induced by electronic structure change.

(Invited) Thermally Oxidized Yttrium Oxide on Germanium for n-Mos Capacitor and Field-Effect Transistor

Germanium (Ge) has many exciting material characteristics, such as high carrier mobility and narrow bandgap in the near-infrared range. Thus it is suitable for various applications. A high-quality insulating film on Ge is required to apply Ge to novel electronic devices successfully. It is well known that GeO2 on Ge has good electrical characteristics as a gate insulator or interlayer (IL), similar to SiO2 on Si [1]. Unlike SiO2, however, GeO2 is thermodynamically unstable under atmospheric pressure at typical oxidation temperatures (~400 °C) and volatilizes as GeO [2,3]. Several methods have been developed to suppress GeO volatilization from the surface. For example, transition metals such as yttrium (Y) have been introduced into GeO2. Yttrium (Y)-doped GeO2 has excellent thermal, chemical, and electrical characteristics. In the capacitance–voltage measurement, it shows a low interface state density (D it) and a narrow hysteresis corresponding to the border trap (BT) density (N bt) of gate insulators [4]. Based on the above studies, we focused on metal Y deposition with subsequent thermal oxidation as an efficient alternative method to deposit Y-oxide as a gate insulator on Ge. This method has been studied to deposit Y2O3 as a gate insulator on Si [5]. Moreover, metal oxidation has been used to form various gate insulators on Ge, such as Al [6] and Hf [7]. In this study, we expect a capping layer of Y and oxidized Y to suppress GeO volatilization and stabilize the interface. We fabricated and evaluated metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors (FETs) with either a thermally oxidized Y or a thermally oxidized Ge oxide layer. The structural analysis found that the insulator was divided into three layers: Y2O3, YGeO3, and GeOx from the top. The oxidation temperature affected only the thickness of the bottom GeOx layer. We found that the Y-oxide gate stack had better electrical characteristics and a lower D it and N bt than the thermally oxidized GeOx insulator. In contrast, the D it–energy distribution and N bt temperature dependence of the Y-oxide gate insulator were similar to those of the GeOx gate insulator. We examined these observations, including the structural analysis results. We found that thermally oxidized Y had a distinct advantage over thermally oxidized Ge oxide: the possibility of controlling the structure and electrical characteristics of the Ge gate stack, such as the GeOx thickness and the BT signal origin.[1] H. Matsubara et al., Appl. Phys. Lett. 93 (2008) 032104. https://doi.org/10.1063/1.2959731[2] S. K. Wang et al., J. Appl. Phys. 108 (2010) 054104. https://doi.org/10.1063/1.3475990[3] S. K. Sahari et al., J. Phys. Conf. Ser. 417 (2013) 012014. https://doi.org/10.1088/1742-6596/417/1/012014[4] C. Lu et al., J. Appl. Phys. 116 (2014) 174103. https://doi.org/10.1063/1.4901205[5] M. Gurvitch et al., Appl. Phys. Lett. 51 (1987) 919. https://doi.org/10.1063/1.98801[6] T. Ohno, et al., Appl. Phys. Lett. 107 (2015) 133107. https://doi.org/10.1063/1.4932385[7] T. Hosoi et al., Microelectron. Eng. 109 (2013) 137. https://doi.org/10.1016/j.mee.2013.03.115[8] W.-C. Wen et al., Mat. Sci. Semicond. Processing, accepted (2023).

Characterization of SiC/SiO<sub>2</sub> Interface State under Different NO Annealing

Interface properties of 4H-SiC N-MOS and P-MOS capacitors with two different NO annealing conditions are characterized by the conductance method. With the enhancement of nitrogen passivation, the density of interface states is reduced as expected. Fast interface states (response frequencies >1 MHz) are observed for both N-MOS and P-MOS capacitors with weak NO passivation. After strong NO passivation, the fast states are passivated to the interface states with lower response frequency in N-MOS and significantly suppressed in P-MOS. It indicates that the nitridation may passivate the defects by shifting them from shallow level to deep level.

Fabrication and characterization of germanium n-MOS and n-MOSFET with thermally oxidized yttrium gate insulator: Formation of underlying germanium oxide and its electrical characteristics

A high-quality insulating film on germanium is essential for germanium applications. In this study, we oxidized metal yttrium at 500–550 °C to generate an yttrium oxide (Y-oxide) layer on germanium. According to transmission electron microscopy images, Y-oxide comprised three layers, which were Y2O3, YGeO3, and GeOx from the top side. n-Type metal-oxide-semiconductor (n-MOS) capacitors and n-type MOS field-effect transistors (n-MOSFETs) with the Y-oxide gate insulator showed typical electrical characteristics. The n-MOS capacitor with the Y-oxide gate insulator had a lower interface state density (Dit) and border trap density (Nbt) than the n-MOS capacitor with a thermally oxidized GeOx insulator, suggesting that defects were terminated by Y atoms in the GeOx layer and GeOx/Ge interface. In contrast, the Dit–energy distribution and Nbt temperature dependence of the Y-oxide gate insulator were similar to those of the GeOx gate insulator, indicating that the defect signals originated in GeOx underlying YGeO3. The structural analysis showed that the temperature of metal yttrium oxidation affected only the GeOx thickness. Therefore, adjusting the conditions of metal yttrium oxidation may produce Y-oxidized gate stacks with a thinner GeOx layer or even direct contact of YGeO3 and Ge, which may result in different Dit values, Nbt values, and Nbt–temperature trends.

Switched-Capacitor Boost-Buck Ladder Converters With Extended Voltage Range in Standard CMOS

This paper presents fully integrated switched-capacitor boost-buck power converters with conversion ratios 5, 7, and 1/5. Such converters operate over a voltage range extended beyond the device ratings due to a low-voltage-stress configuration, accumulation-mode NMOS capacitors, and a circuit technique for switch bootstrapping. After modeling the simple and the symmetrical ladder converters, we determined methods for assessing the device working voltages and for optimizing the sizes of capacitors and switches. The key performance parameters were compared and the losses due to non-linear parasitic capacitances were calculated. The characterization of the prototypes in a 1.8-3.3-V, 0.18-$\mu \text{m}$ CMOS process demonstrated a 15 V range, a 5.4 mW/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> output power density, and good correlation between measured and predicted results.

Radiation tolerance, charge trapping, and defect dynamics studies of ALD-grown Al/HfO2/Si nMOSCAPs

The radiation response, long-term performance, and reliability of HfO2-based gate dielectric materials play a critical role in metal oxide semiconductor (MOS) technology for space device applications. Al/HfO2/Si atomic layer-deposited devices were irradiated by gamma and swift heavy ions. An increase in the leakage current and charge trapping has been observed as the gamma irradiation dose varied from 25 to 100 krad. The density of oxide traps is found to increase with an increase in the gamma dose while the interface trap density is found to decrease. Another set of samples were irradiated by 120 MeV Au ions to study the SHI-induced defect annealing/creation of defects and intermixing effects in HfO2/Si-based devices. The formation of an interfacial layer of HfSiO at a fluence of at 5 × 1013 cm−2 is revealed by X-ray reflectivity analysis. The densities of interface- and oxide-trapped charges are found to decrease up to a critical fluence of 1 × 1012 cm−2 and then increase with further increase in fluence to 5 × 1013 cm−2. The presence of the interlayer, due to the swift heavy ion-induced intermixing, has been confirmed by X-ray photoelectron spectroscopy measurements. Various current conduction mechanisms in both substrate and gate injection cases were used to understand the basic mechanisms of direct, Fowler–Nordheim, and Poole–Frenkel tunneling, as well as Schottky emission in these devices. These studies elucidated the radiation tolerance and charge-trapping behavior of Al/HfO2/Si nMOS capacitors.

Large initial flatband voltage shifts in HfSiO2 high-k charge trapping memory

The impact of top blocking layers on initial flatband voltage are investigated in nMOS capacitors with a HfSiO2 charge-trapping layer for high-k charge trapping memory. We found that an initial flatband voltage that significantly affects the programing properties largely depends on the structure of the top blocking layers such as Al2O3 and stacked Al2O3/SiON/Al2O3. Our experimental results on the thickness dependence of each layer indicate that the initial flatband shift is related to oxygen vacancy formation in the HfSiO2 charge-trapping layer. The SiON thickness in the top blocking layer is a key factor in the control of the initial flatband voltage.

A low-jitter all-digital PLL with high-linearity DCO

This paper describes a low-jitter all-digital phase-locked loop (ADPLL) with a high-linearity digitally controlled oscillator (DCO). The proposed DCO consists of a three-stage differential ring oscillator with a coarse-tune stage, a fine-tune stage, and process voltage temperature (PVT) variation compensation. The coarse-tune stage comprises tri-inverters controlled using the binary-weighted method and has high linearity and monotonicity. The fine-tune stage consists of six groups of NMOS capacitors to achieve a high timing resolution. Moreover, the range of the DCO frequency can be varied according to the PVT variations s to match the desired frequency range of the ADPLL. The proposed ADPLL was implemented in a 0.18-µm standard CMOS process with a supply voltage of 1.8 V. The experimental results indicated that the proposed DCO can cover the frequency range of 202–518 MHz under different PVT variations. The output frequency range of the proposed ADPLL with a programmable divider was 402–417 MHz, and its division range was 134–139. The ADPLL is suitable for MedRadio band applications. At 411 MHz, the power consumption was 13 mW, rms jitter was 5.98 ps (0.25% of the output period), and active die area was 0.27 mm2.

Improved channel mobility of 4H-SiC n-MOSFETs by ultrahigh-temperature gate oxidation with low-oxygen partial-pressure cooling

An n-channel metal–oxide–semiconductor field-effect transistor (MOSFET) with high field-effect mobility (μFE) on 4H-SiC (0001) was fabricated using an ultrahigh-temperature gate-oxidation technique, and its improved channel mobility was demonstrated by employing a low-oxygen partial-pressure cooling procedure. The ideal flatband voltage for n-MOS and p-MOS capacitors and hysteresis-free drain current–gate voltage (Id–Vg) characteristics were obtained through gate oxidation at 1450 °C in 100% O2 ambient at 1 atm followed by the low-oxygen partial-pressure (1%) rapid-cooling procedure. From the Id–Vg characteristics, a μFE of 15.8 cm2 V−1 s−1 was obtained under the pure O2 gate-oxidation process.

Analysis of Interface Trap Density and Channel Mobility in 4H-SiC NMOS Capacitors and Lateral MOSFETs

Lateral implanted SiC MOSFETs and NMOS capacitors were fabricated and used to extract channel mobility and interface state density DIT for three different gate oxides. DIT values were extracted using the high(1 MHz)-low(1 kHz) method for NMOS capacitors and the subthreshold slope for MOSFETs. The subthreshold slope extraction gave 6-20 times higher DIT values compared to the high-low method, presumably because the high-low method cannot capture the fastest traps [1]. None of the methods resulted in clear proportionality between the inverse channel mobility and DIT. The subthreshold slope gave similar DIT values for samples with different surface p-doping concentrations indicating that the method is not sensitive to the threshold voltage.

Electrical Stability Impact of Gate Oxide in Channel Implanted SiC NMOS and PMOS Transistors

Operation of SiC MOSFETs beyond 300°C opens up opportunities for a wide range of CMOS based digital and analogue applications. However the majority of the literature focuses only on the optimization of a single type of MOS device (either PMOS or more commonly NMOS) and there is a lack of a comprehensive study describing the challenge of optimizing CMOS devices. This study reports on the impact of gate oxide performance in channel implanted SiC on the electrical stability for both NMOS and PMOS capacitors and transistors. Parameters including interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) and effective charge (NEFF) have been acquired from C-V characteristics to assess the effectiveness of the fabrication process in realising high quality gate dielectrics. The performance of SiC based CMOS transistors were analyzed by correlating the characteristics of the MOS interface properties, the MOSFET 1/f noise performance and transistor on-state stability at 300°C. The observed instability of PMOS devices is more significant than in equivalent NMOS devices. The results from MOS capacitors comprising interface state density (Dit), flatband voltage (VFB), threshold voltage (VTH) for both N and P MOS are in agreement with the expected characteristics of the respective transistors.

High-Efficiency E-Band Power Amplifiers and Transmitter Using Gate Capacitance Linearization in a 65-nm CMOS Process

This brief presents a new design technique for high-efficiency CMOS millimeter-wave power amplifiers (PAs) and the implementations of a two-stage moderate-power PA, a three-stage high-power PA, and a transmitter all working over 68–78 GHz. The proposed PAs adopt nMOS capacitors connected at the gates of the transistors of the last one or two amplifying stages to compensate for the gate capacitance variation over a large signal swing, thus improving the linearity and the power efficiency. Implemented in a 65-nm CMOS process, the two-stage PA achieves a peak power-added efficiency (PAE) of 24.2%, a maximum gain of 17 dB, and a 3-dB bandwidth from 68 to 78 GHz. The three-stage PA achieves a saturated power (Psat) of 17.3 dBm, a peak PAE of 18.9%, and a maximum gain of 21.4 dB. The transmitter consisting of the three-stage PA and a passive double-balanced mixer with local oscillator shaping technique achieves a Psat of 14.6 dBm, a peak efficiency of 13.9%, and a conversion gain of 15.6 dB.

Impact of N2O/NH3/N2 Gas Mixture on the Interface Quality of Germanium MOS Capacitors

The development of high quality germanium based devices has been generating a lot of interest due to the excellent optical and electrical properties of germanium [1-4]. From an optical perspective germanium has high index of refraction, low optical dispersion, and the possibility to tune the silicon physical properties and reduce the band gap by controlling Ge content which makes it very useful for photo-detectors application. Furthermore, the bulk hole and electron mobility of Ge are approximately four and two times higher than conventional Si channel, respectively, which makes it an excellent candidate for future high performance complementary metal-oxide-semiconductor (CMOS) devices. The major weaknesses in Ge technology is germanium oxide (GeO and GeO2) stability and water solubility, the poor quality of Ge/ high κ-dielectric interfaces and the difficulty in forming a low-Dit (density of traps) Ge metal-oxide-semiconductor interface. However, a superior high-k/Ge gate stack satisfying low Dit and thin EOT simultaneously is mandatory for high performance Ge-channel devices. Several techniques have been adopted for Ge interface passivation, among them the oxygen-based passivation such as GeOx which has been proved to be thermally unstable, while nitrogen-based passivation has better thermal stability. Furthermore, the energy needed to break the nitrogen-oxygen bond is smaller than that of oxygen-oxygen bond in O2 plasma which makes nitration-based passivation a low temperature technique and compatible with Ge MOSFET fabrication. In this paper a mixture of N2O, NH3 and N2passivation on Ge is performed using RF-PECVD reactor and extensively studied in terms of Ge MOS capacitor. In order to fabricate Ge MOS capacitor a P-type (100) Ge substrate with a resistivity of (5-10) mΩ.cm is cleaned by diluted 1:10 BHF solution. After being cleaned the samples is loaded immediately to an Oxford Instruments System 100 PECVD tool at RF frequency of 13.56MHz.The plasma power was fixed at 20W and a 710 sccm flow of N2O for 2min is used in all treated samples as a pre plasma clean step. After this 380 sccm of N2 and 30 sccm of NH3 were performed at 285 ºC and pressure of 1T at different exposure time on top of the Ge surface. A sample without passivation is fabricated as a control sample. A 5nm thin film of HfO2 was deposited by plasma- Atomic Layer Deposition (ALD) at 200 ºC, followed by Al deposition using e-beam evaporator through a shadow mask to define the gates. Finally, post dielectric annealing was carried out at 400 ºC for 10min under forming gases. Capacitance-Voltage (C-V) measurements are carried out using Agilent B 1505 A curve tracer + Signatone manual 1160 prober. Fig. 1 shows a schematic of the fabricated gate stack and Fig. 2 shows the typical C–V characteristics of nMOS capacitors without (a) and (b), (c) and (d) with N2O/NH3/N2 treatment at different exposure time. As can be seen from Fig.2 the hump is invisible for the samples passivated by N2O/NH3/N2, indicating that the formed GeOxNy IL may block the impurities from diffusing from the gate dielectric into the Ge substrate. Furthermore, the hysteresis of metal–oxide–semiconductor (MOS) capacitor with HfO2 serving as gate dielectric is reduced to ~150 mV, compared with ~400mV mV of the untreated one. Moreover, this passivation technique can act as an effective method for high performance NMOSFET devices. 1. R.Cariou, R.Ruggeri, X.Tan, Giovanni Mannino, J.Nassar, and P.Roca I Cabarrocas, structural properties of relaxed thin film germanium layers grown by low temperature RF-PECVD epitaxy on Si and Ge (100) substrate, AIP Advances 4,077103 (2014). 2. Ammar Nayfeh, Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si, IEEE ELECTRON DEVICE LETTERS, 26 (9), 2005. 3. Ali K Okyay, Ammar M Nayfeh, Krishna C Saraswat, Takao Yonehara, Ann Marshall, Paul C McIntyre, High-efficiency metal–semiconductor–metal photodetectors on heteroepitaxially grown Ge on Si, Optics Letter, 31(17), 2006. 4. Mahmoud S Rasras, Douglas M Gill, Mark P Earnshaw, Christopher R Doerr, Joseph S Weiner, Cristian Bolle, Young-Kai Chen, CMOS silicon receiver integrated with Ge detector and reconfigurable optical filter,IEEE photonic Technology Letters, 22(2), 2010. Figure 1

Time Resolved Gate Oxide Stress of 4H-SiC Planar MOSFETs and NMOS Capacitors

Lateral SiC MOSFETs and NMOS capacitors were fabricated and electrically evaluated for channel mobility, DIT and gate oxide breakdown. Time resolved measurements of VTH and VFB drift during gate bias stress were performed resulting in logarithmic time dependence for moderate stress time and temperature. Gate bias stress was also carried out during 20 hours at temperatures up to 225 C. Stress times resulting in a VTH shift of 500 mV were determined and an activation energy EA=0.86 eV was extracted for the VTH drift.

Analytical Evaluation of Thermally Oxidized and Deposited Dielectric in NMOS-PMOS devices

We demonstrate the influence of enhancing the dielectric film used to form the gate in complimentary MOS circuits, designed for high temperature operation. The data show that the characteristics of both n-MOS and p-MOS capacitors and transistors have degraded capacitance characteristics in terms of the trapped charge in the dielectric, although the interface state density is dictated by the underlying stub oxide, at around 5×1012 cm-2eV-1. The use of a deposited oxide also reduces the variability in the critical electric field in the oxide, whilst maintaining a value of approximately 10MV cm-1. The channel mobility extracted from n-and pMOS transistors fabricated alongside the capacitors showed similar values, of approximately 3.8 cm2V-1s-1, which are limited by the high doping level in the epilayers used in this study.

DLTS analysis of amphoteric interface defects in high-TiO2 MOS structures prepared by sol-gel spin-coating

High-κ TiO2 thin films have been fabricated from a facile, combined sol – gel spin – coating technique on p and n type silicon substrate. XRD and Raman studies headed the existence of anatase phase of TiO2 with a small grain size of 18 nm. The refractive index ‘n’ quantified from ellipsometry is 2.41. AFM studies suggest a high quality, pore free films with a fairly small surface roughness of 6 Å. The presence of Ti in its tetravalent state is confirmed by XPS analysis. The defect parameters observed at the interface of Si/TiO2 were studied by capacitance – voltage (C – V) and deep level transient spectroscopy (DLTS). The flat – band voltage (VFB) and the density of slow interface states estimated are – 0.9, – 0.44 V and 5.24×1010, 1.03×1011 cm−2; for the NMOS and PMOS capacitors, respectively. The activation energies, interface state densities and capture cross – sections measured by DLTS are EV + 0.30, EC – 0.21 eV; 8.73×1011, 6.41×1011 eV−1 cm−2 and 5.8×10−23, 8.11×10−23 cm2 for the NMOS and PMOS structures, respectively. A low value of interface state density in both P- and N-MOS structures makes it a suitable alternate dielectric layer for CMOS applications. And also very low value of capture cross section for both the carriers due to the amphoteric nature of defect indicates that the traps are not aggressive recombination centers and possibly can not contribute to the device operation to a large extent.

Reliable Antifuse One-Time-Programmable Scheme With Charge Pump for Postpackage Repair of DRAM

A reliable antifuse (AF) one-time-programmable (OTP) cell and its sensing plus programming circuits for postpackage repair of dynamic random access memory (DRAM) are presented. The OTP cell was fabricated without any process modifications by utilizing destructive breakdown of thin gate oxide of nMOS capacitor as storage. The measurement results of OTP array fabricated by 0.13- $\mu $ m CMOS process show a tight read current distribution after programming. For pin compatibility with standard DRAM specifications, an internal charge pump is designed to provide high program voltage without any additional pin. Based on the AF cells, a programmable decoder is proposed to store the address of failed bit, decode the input address, and decide whether to access normal bit or redundant one of DRAM. The whole bit-repair scheme uses static latches as redundant cells. By avoiding the uses of address comparator and multiplexer, the proposed scheme shows less access penalty compared with prior scheme.

Nanostructural defects evidenced in failing silicon-based NMOS capacitors by advanced failure analysis techniques

STMicroelectronics, Avenue C´elestin Coq, 13106 Rousset, FranceReceived: 25 August 2013 / Received in final form: 11 February 2014 / Accepted: 6 March 2014Published online: 21 April 2014 – ⃝c EDP Sciences 2014Abstract. An experimental methodology compliant with industrial constraints was deployed to uncover theorigin of soft breakdown events in large planar silicon-based NMOS capacitors. Complementary advancedfailure analysis techniques were advantageously employed to localize, isolate and observe structural defectsat nanoscale. After an accurate localization of the failing area by optical beam-induced resistance change(OBIRCH), focused ion beam (FIB) technique enabled preparing thin specimens adequate for transmissionelectron microscopy (TEM). Characterization of the gate oxide microstructure was performed by high-resolution TEM imaging and energy-filtered spectroscopy. A dedicated experimental protocol relying oniterative FIB thinning and TEM observation enabled improving the quality of electron imaging of defectsat atom scale. In that way, the gate oxide integrity was evaluated and an electrical stress-induced siliconepitaxy was detected concomitantly to soft breakdown events appearing during constant voltage stress.The growth of silicon hillocks enables consuming a part of the breakdown energy and may prevent the softbreakdown event to evolve towards a hard breakdown that is catastrophic for device functionality.

First demonstration of device-quality symmetric N-MOS and P-MOS capacitors on p-type and n-type crystalline Ge substrates

Ge interface nitride passivation.Si passivation layer thickness.SiON surface on Si passivation layer.Anneal to eliminate Ge-N bonds.Symmetric NMOS and CMOS capacitors. Three significant issues with respect to the ultimate scaling limitations of CMOS devices are (i) the channel or transport material, (ii) high-? compatible gate stacks: (a) the interface with the semiconductor substrate; (b) the high dielectrics, and (c) the gate metal, and (iii) the topological structure, planar, nano-tube, or in, etc. Two of these are high-lighted, focusing on (i) crystalline Ge, and transition metal dielectrics including specifically non-crystalline Hf Si oxynitrides, and nano-grain (a) ultra-thin 2nm thick HfO2 and TiO2. The research has demonstrated shallow trap interfacial slow trap densities of ~5i?1010cm-2, no detectable negative bulk fixed charges, and symmetric N- and P-MOCAPS in planar geometries. EOT values <0.5nm were obtained for low-leakage current for N-MOSCAPS with ng-TiO2 in contact with plasma processed c-Ge substrates.

Research on the capacitance-voltage characteristic of strained-silicon NMOS accumulation capacitor

Accumulation MOS capacitor is more linear than inversion MOS capacitor and is almost independent of the operation frequency. In this paper, we present first the formation mechanism of the plateau, observed in the C-V characteristic of the strained-Si NMOS capacitor, and then a physical model for strained-Si NMOS capacitor in accumulation region. The results from the model show to be in excellent agreement with the experimental data. The proposed model can provide valuable reference for the strained-Si device design, and is has been implemented in the software for extracting the parameter of strained-Si MOSFET.