First demonstration of device-quality symmetric N-MOS and P-MOS capacitors on p-type and n-type crystalline Ge substrates

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Ge interface nitride passivation.Si passivation layer thickness.SiON surface on Si passivation layer.Anneal to eliminate Ge-N bonds.Symmetric NMOS and CMOS capacitors. Three significant issues with respect to the ultimate scaling limitations of CMOS devices are (i) the channel or transport material, (ii) high-? compatible gate stacks: (a) the interface with the semiconductor substrate; (b) the high dielectrics, and (c) the gate metal, and (iii) the topological structure, planar, nano-tube, or in, etc. Two of these are high-lighted, focusing on (i) crystalline Ge, and transition metal dielectrics including specifically non-crystalline Hf Si oxynitrides, and nano-grain (a) ultra-thin 2nm thick HfO2 and TiO2. The research has demonstrated shallow trap interfacial slow trap densities of ~5i?1010cm-2, no detectable negative bulk fixed charges, and symmetric N- and P-MOCAPS in planar geometries. EOT values <0.5nm were obtained for low-leakage current for N-MOSCAPS with ng-TiO2 in contact with plasma processed c-Ge substrates.