A low-jitter all-digital PLL with high-linearity DCO

Abstract

This paper describes a low-jitter all-digital phase-locked loop (ADPLL) with a high-linearity digitally controlled oscillator (DCO). The proposed DCO consists of a three-stage differential ring oscillator with a coarse-tune stage, a fine-tune stage, and process voltage temperature (PVT) variation compensation. The coarse-tune stage comprises tri-inverters controlled using the binary-weighted method and has high linearity and monotonicity. The fine-tune stage consists of six groups of NMOS capacitors to achieve a high timing resolution. Moreover, the range of the DCO frequency can be varied according to the PVT variations s to match the desired frequency range of the ADPLL. The proposed ADPLL was implemented in a 0.18-µm standard CMOS process with a supply voltage of 1.8 V. The experimental results indicated that the proposed DCO can cover the frequency range of 202–518 MHz under different PVT variations. The output frequency range of the proposed ADPLL with a programmable divider was 402–417 MHz, and its division range was 134–139. The ADPLL is suitable for MedRadio band applications. At 411 MHz, the power consumption was 13 mW, rms jitter was 5.98 ps (0.25% of the output period), and active die area was 0.27 mm2.