Abstract
In this paper, a 0.5V/1.0V low-power all-digital phase-locked loop (ADPLL) for battery-powered devices with a dynamic voltage and frequency scaling (DVFS) scheme is presented. The proposed frequency estimation algorithm with a fine-resolution monotonic response digitally controlled oscillator (DCO), can quickly calculate the target control code for the DCO, and thus, the ADPLL can achieve a fast lock time in four clock cycles. The proposed ADPLL is implemented in a standard performance 65nm CMOS process with standard cells. The power consumption is 52.69μW at 600MHz with a 0.5V power supply and is 1.26mW at 1.28GHz with a 1.0V supply.
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