Multistage Interconnection Networks Research Articles

Optical interconnection reverse data vortex network: performance analysis

Multistage interconnection networks are employed in data centres to interchange information between the processors and memory elements. Data Vortex (DV) is a multistage minimum logic network which can be used in data centres. DV satisfies the requirements of the interconnection networks such as scalability and throughput. However, the latency is on higher side, and reduction in latency can lead to higher throughput. In the present paper, we describe the feasibility and performance analysis of DV architecture in reverse direction. The routing and the possible hardware model of the node switch have been discussed. We present the performance analysis of Reverse Data Vortex (RDV) architecture in terms of throughput, latency and latency distribution. A comparative study with DV on throughput, latency and latency distribution is also presented. The simulation result shows that the decrease in latency of RDV is about 50 % that of DV and this leads to an increase in injection rate of RDV to values more than two times that of DV.

Message Broadcasting via a New Fault Tolerant Irregular Advance Omega Network in Faulty and Nonfaulty Network Environments

Interconnection Network (IN) is a key element for all parallel processing applications. Multistage Interconnection Network (MIN) is an efficient IN for these applications, as it has the quality of excellent performance at low cost with high reliability. MINs are effective medium for message broadcasting. Doing the same task in faulty situations is a critical challenge. In this paper, we have presented a new Fault Tolerant Interconnection Network named as Irregular Advance Omega Network (IAON); also we have presented its routing algorithm. IAON is the modified form of Advance Omega Network. The proposed MIN can endure multiple faults and provides a suitable path between every source to every destination. We have examined the fault tolerance capacity of IAON and compared its performance with other existing MINs. In order to check the performance of proposed MIN, message broadcasting was performed in three conditions as follows: (1) when network was fault free; (2) when network was Single Switch Faulty in every stage; (3) when network was Double Switch Faulty in every stage. Results showed that IAON performed better than the earlier proposed MINs.

ZeroX Algorithms with Free crosstalk in Optical Multistage Interconnection Network

Multistage interconnection networks (MINs) have been proposed as interconnecting structures in various types of communication applications ranging from parallel systems, switching architectures, to multicore systems and advances. Optical technologies have drawn the interest for optical implementation in MINs to achieve high bandwidth capacity at the rate of terabits per second. Crosstalk is the major problem with optical interconnections; it not only degrades the performance of network but also disturbs the path of communication signals. To avoid crosstalk in Optical MINs many algorithms have been proposed by many researchers and some of the researchers suppose some solution to improve Zero Algorithm. This paper will be illustrated that is no any crosstalk appears in Zero based algorithms (ZeroX, ZeroY and ZeroXY) in using refine and unique case functions. Through simulation modeling, the Zero based algorithm approach yields the best performance in terms of minimal routing time in and number of passes comparison to the previous algorithms tested for comparison in this paper.

Modelling and performance study of finite-buffered blocking multistage interconnection networks supporting natively 2-class priority routing traffic

In this paper, we model, analyze and evaluate the performance of a 2-class priority architecture for finite-buffered multistage interconnection networks (MINs). The MIN operation modelling is based on a state diagram, which includes the possible MIN states, transitions and conditions under which each transition occurs. Equations expressing state and transition probabilities are subsequently given, providing a formal model for evaluating the MIN's performance. The proposed architecture's performance is subsequently analyzed using simulations; operational parameters, including buffer length, MIN size, offered load and ratios of high priority packets which are varied across experiments to gain insight on how each parameter affects the overall MIN performance. The 2-class priority MIN performance is compared against the performance of single priority MINs, detailing the performance gains and losses for packets of different priorities. Performance is assessed by means of the two most commonly used factors, namely packet throughput and packet delay, while a performance indicator combining both individual factors is introduced, computed and discussed. The findings of this study can be used by network and interconnection system designers in order to deliver efficient systems while minimizing the overall cost. The performance evaluation model can also be applied to other network types, providing the necessary data for network designers to select optimal values for network operation parameters.

Design and Implementation of Multistage Interconnection Networks for SoC Networks

In this paper the focus is on a family of Interconnection Networks (INs) known as Multistage Interconnection Networks (MINs). When it is exploited in Network-on-Chip (NoC) architecture designs, smaller circuit area, lower power consumption, less junctions and broader bandwidth can be achieved. Each MIN can be considered as an alternative for an NoC architecture design for its simple topology and easy scalability with low degree. This paper includes two major contributions. First, it compares the performance of seven prominent MINs (i.e. Omega, Butterfly, Flattened Butterfly, Flattened Baseline, Generalized Cube, Benes and Clos networks) based on 45nm-CMOS technology and under different types of Synthetic and Trace-driven workloads. Second, a network called Meta-Flattened Network (MFN), was introduced that can decrease the blocking probability by means of reduction the number of hops and increase the intermediate paths between stages. This is also led into significant decrease in power consumption.

Class-based weighted fair queuing scheduling on quad-priority Delta Networks

Contemporary networks support multiple priorities, aiming to differentiate the quality of service (QoS) levels offered to individual traffic classes. Support for multiple priorities necessitates the introduction of a scheduling algorithm, to select each time the next packet to transmit over the data link. Class-based weighted fair queuing (CBWFQ) scheduling and its variations are widely used as a scheduling technique since it is easy to implement and prevent the low-priority queues from starvation, i.e. receiving no service during periods of high-priority traffic. CBWFQ effectively thus offers low-priority queues, the opportunity to transmit packets even though the high-priority queues are not empty. In this paper, we present the modelling and performance evaluation of a single-buffered, four-priority multistage interconnection network (MIN) operating under the CBWFQ scheduling policy. Performance evaluation is conducted through simulation, and the performance metrics obtained can be used by MIN designers to set the appropriate queue weights according to the expected traffic and the desired QoS levels for each priority class, delivering efficient thus systems.

Progressive Congestion Management Based on Packet Marking and Validation Techniques

Congestion management in multistage interconnection networks is a serious problem, which is not solved completely. In order to avoid the degradation of network performance when congestion appears, several congestion management mechanisms have been proposed. Most of these mechanisms are based on explicit congestion notification. For this purpose, switches detect congestion and depending on the applied strategy, packets are marked to warn the source hosts. In response, source hosts apply some corrective actions to adjust their packet injection rate. Although these proposals seem quite effective, they either exhibit some drawbacks or are partial solutions. Some of them introduce some penalties over the flows not responsible for congestion, whereas others can cope only with congestion situations that last for a short time. In this paper, we present an overview of the different strategies to detect and correct congestion in multistage interconnection networks, and propose a new mechanism referred to as Marking and Validation Congestion Management (MVCM), targeted to this kind of lossless networks, and based on a more refined packet marking strategy combined with a fair set of corrective actions, that makes the mechanism able to effectively manage congestion regardless of the congestion degree. Evaluation results show the effectiveness and robustness of the proposed mechanism.

Terminal reliability assessment of gamma and extra‐stage gamma networks

Purpose – Multistage Interconnection Networks (MINs) are a class of network systems designed to improve communication in large‐scale parallel processing systems. These networks facilitate the communications to perform a single overall task in a parallel processing system consisting of a large number of processors that are working together. The purpose of this paper is to discuss two types of MINs: gamma networks and extra‐stage gamma networks. It is shown that a specific modification in the structure of a standard gamma network will add multiple paths from a specific source to a specific destination.Design/methodology/approach – The terminal reliability of these networks are evaluated and analyzed in terms of the number of their paths connecting a source i, i=1, 2, … , N to any terminal. Numerical examples are also given to demonstrate each network's performance.Findings – In this paper, terminal reliability as a function of the reliability of a switching element of MINs is analyzed. Terminal reliability,...

An analytical model for the performance evaluation of multistage interconnection networks with two class priorities

The aim of this paper is to develop an analytical method for performance evaluation of double prioritized Multistage Interconnected Networks (MINs) with single or multilayers and backpressure operation which provide service differentiation and QoS guarantee to an end application running over next generation Internet or Grid systems. Specifically, a new architecture of switching elements is used for the construction of MINs. This switch element uses two parallel queues in order to serve dual priority traffic. Besides this, uniform traffic conditions are presupposed and the bulk of packet arrivals in each cycle to the network inputs follow a Bernoulli distribution. A new analytical model for evaluating single buffered MIN’s with 2×2 special switching elements supporting internally two classes’ priority traffic is presented. Equations for the steady state are derived. These equations are then used in finding the most important multistage network performance metrics, such as throughput, and packet latency. The results are also validated using simulation and compared with previous related work in marginal cases. This proposed analytical model is accurate for various network sizes and various values of offered traffic to the multistage network inputs.

Optical Interconnection Networks Based on Microring Resonators

Optical microring resonators can be integrated on a chip to perform switching operations directly in the optical domain. Thus they become a building block to create switching elements in on-chip optical interconnection networks, which promise to overcome some of the limitations of current electronic networks. However, the peculiar asymmetric power losses of microring resonators impose new constraints on the design and control of on-chip optical networks. In this work, we study the design of multistage interconnection networks optimized for a particular metric that we name the degradation index, which characterizes the asymmetric behavior of microrings. We also propose a routing control algorithm to maximize the overall throughput, considering the maximum allowed degradation index as a constraint.

Design and control of next generation distribution frames

In today’s access networks, the permutation of circuits connecting the subscriber lines to Plain Old Telephone Service (POTS) and to Digital Subscriber Line Access Multiplexers (DSLAMs) occurs in the Main Distribution Frame (MDF) and is still manually configured. However, new market regulations and new policies adopted by operators require increasingly more frequent permutations, making the manual configuration activity particularly expensive. Very recently, Automated MDFs (AMDFs) have been developed to provide inexpensive and almost real-time switching capability. Our study, based on more than 50years of research activities on architectures for circuit switching, is focused on overcoming the limits of classical architectures. In fact, strictly non-blocking multistage networks are too expensive, as a consequence of the large number of ports they require (sometimes exceeding 100,000). In addition, rearrangeable multistage networks can temporarily interrupt active circuits, affecting the performance of ADSL subscriber lines.As a possible solution to these problems, we propose the design of AMDFs based on Non-Interruptive Rearrangeable (NIR) networks. We show how to optimize the routing control to minimize the setup time of a circuit and to exploit output grouping. We believe that the solution described above is not only relevant for the theory of multistage interconnection networks, but also for the design and operation of large AMDFs.

MULTISTAGE INTERCONNECTION NETWORKS: A TRANSITION TO OPTICAL

Several types of interconnection networks have been proposed for parallel processing. One of them is MIN’s (Multistage interconnection networks). With the better way of communication between processor and memory, MIN’s are less complex, good fault tolerance, high reliability, fast in communication and low cost. To achieving reliable, fast and flexible communication optical communication are necessary. Through optical networks we can achieve high performance and low latency also. With their great advantages over electronic networks, OMIN’s also having their own demands and problems. This paper focuses on the qualities of Optical MINs. Here we compare Optical MINs with electronic MIN’s with their design issues and gives some solution approaches for optical MINs to solve crosstalk.

Design and Reliability Analysis of a Class of Irregular Fault-Tolerant Multistage Interconnection Networks

llel processing can be used to design high performance computing systems. In a parallel computer inter-connecting processors and linking them efficiently to the memory modules is not an easy task. Therefore, there is a requirement of an interconnection network that provides the desired connectivity and performance at minimum cost. Multistage interconnection networks (MINs) provide cost-effective, high- bandwidth communication between processors and/or memory modules in comparison to bus and crossbar interconnection networks. In this paper a new irregular MIN named IFTN (Improved Four Tree Network) has been proposed. The performance of IFTN has been measured in terms of reliability and cost. It has been proved that the proposed network IFTN provides much better fault-tolerance and reliability at lesser cost In Comparison To Four Trees.

Reliability Analysis of Multi Path Multistage Interconnection Networks

As systems have grown more complex, the consequences on their reliable behavior have become severe in terms of cost, life, size etc, and the interest in accessing system reliability and the need for improving the reliability of systems have become very important. This paper presents an analytical model for the reliability evaluation of multipath multistage interconnection networks (MINs). In order to define the fault tolerance, behavior of various multi path MIN networks has been introduced. The results are compared and discussed.

Novel Method For Blocking Diagnosis In Baseline Network

Multistage Interconnection Networks which are based on the connection switches are used to connect processors and memories in the parallel computer systems. There networks are classified into Blocking and Non Blocking Networks. In Blocking MINS, Blocking on the switches is very essential. Baseline network is one of the various Blocking MINS. If a permutation Factor is applied to a baseline network, and no problem is occurred in terms of blocking, we will regard that permutation as admissible otherwise it will be considered as inadmissible. In this paper, a method is presented for a quick and systematic diagnosis of an admissible permutation in the baseline network that can diagnose switches in case of applying an inadmissible permutation to a block network so that with the help of fault tolerance procedures, a way is prepared for complete and correct transmission of each desired permutation (PE). Hence, in this way, the most fundamental problem of the baseline network, that is its blocking will be diagnosed.

Modified Fault Tolerant Double Tree Network-2

Interconnection networks are constructed to provide interprocess communication. These Networks are compared on the basis of Fault tolerance, Reliability, Path length and cost effectiveness. An irregular class of Fault Tolerant Multistage Interconnection Network (MIN) called Modified Four Double Tree Network-2 (MFDOT-2) is proposed.MFDOT-2 is constructed on the basis of FDOT-2 [1]. The Reliability, Path length and cost effectiveness of some popular irregular class of Multistage Interconnection Networks along with proposed MFDOT-2 is also analyzed.

On Asymptotic Analysis of Packet and Wormhole Switched Routing Algorithm for Application‐Specific Networks‐on‐Chip

The application of the multistage interconnection networks (MINs) in systems‐on‐chip (SoC) and networks‐on‐chip (NoC) is hottest since year 2002. Nevertheless, nobody used them practically for parallel communication. However, to overcome all the previous problems, a new method is proposed that uses MIN to provide intra‐(global) communication among application‐specific NoCs in networks‐in‐package (NiP). For this, four O(n)2 fault‐tolerant parallel algorithms are proposed. It allows different NoCs to communicate in parallel using either fault‐tolerant irregular Penta multistage interconnection network (PNN) or fault‐tolerant regular Hexa multistage interconnection network (HXN). These two are acting as an interconnects‐on‐chip (IoC) in NiP. Both IoC use packet switching and wormhole switching to route packets from source NoC to destination NoC. The results are compared in terms of packet losses and wormhole switching which comes out to be better than packet switching. The comparison of IoC on cost and MTTR concluded that the HXN has the higher cost than the PNN, but MTTR values of the HXN are low in comparison to the PNN. This signifies that the ability to tolerate faults and online repairing of the HXN is higher and faster than the PNN.

Class-Based Weighted Fair Queuing Scheduling on Dual-Priority Delta Networks

Contemporary networks accommodate handling of multiple priorities, aiming to provide suitable QoS levels to different traffic classes. In the presence of multiple priorities, a scheduling algorithm is employed to select each time the next packet to transmit over the data link. Class-based Weighted Fair Queuing (CBWFQ) scheduling and its variations is widely used as a scheduling technique, since it is easy to implement and prevents the low-priority queues from being completely neglected during periods of high-priority traffic. By using this scheduling, low-priority queues have the opportunity to transmit packets even though the high-priority queues are not empty. In this work, the modeling, analysis and performance evaluation of a single-buffered, dual-priority multistage interconnection network (MIN) operating under the CBWFQ scheduling policy is presented. Performance evaluation is conducted through simulation, and the performance measures obtained can be valuable assets for MIN designers, in order to minimize the overall deployment costs and delivering efficient systems.

A Challenge for Routing Algorithms in Optical Multistage Interconnection Networks

Problem statement: A class of dynamic interconnection networks is Multistage Interconnection Networks (MINs) that connects input devices to output devices through a number of switch stages. MINs have assumed importance in recent years; because of their cost-effectiveness. Optical MINs are one type of MINs that have large transmission capacity in the communication networks. There is a major problem in Optical MIN that is crosstalk, which is caused by coupling two signals within a switching element. Approach: To avoid crosstalk in Optical MINs many algorithms have been proposed by many researchers that we review applying five routing algorithms and scheduling them in the Optical MINs. Results: The comparative results of routing algorithms show affective of avoiding crosstalk in number of passes and execution time for different algorithm. Conclusion: The challenge between these routing algorithms is thoroughly investigated, by applying them on Optical MIN and showing which algorithm has better performance to avoid crosstalk.

Modelling and performance evaluation of a novel internal-priority routing scheme for finite-buffered multistage interconnection networks

In this paper, the modelling, analysis and performance evaluation of a novel architecture for internal-priority finite-buffered multistage interconnection networks (MINs) are presented. We model the proposed architecture giving the details of its operation and describing its states and detailing conditions and effects of state transition; we also provide a formal model for evaluating its performance. The proposed architecture's performance is subsequently analysed under the uniform traffic condition, considering various offered loads, buffer lengths and MIN sizes, using simulations. We compare the internal-priority scheme vs. the non-priority (or single priority) scheme, by gathering metrics for the two most important network performance factors, namely, packet throughput and the mean time a packet needs to traverse the network. We demonstrate and quantify the improvements on MIN performance stemming from the introduction of priorities in terms of throughput and a combined performance indicator which depicts the overall performance of the MIN. These performance measures can be valuable assets for designers of parallel multiprocessor systems and networks in order to minimise the overall deployment costs and delivering efficient systems.