Multistage Interconnection Networks Research Articles

A new approach to improve reliability of the multistage interconnection networks

Because of their cost-effectiveness, multistage interconnection networks are widely used in parallel multiprocessor systems to make a connection among the processors and memory modules. One of the most important requirements for these communication systems is reliability. Adding a number of stages to these networks is one of the main approaches to promote this issue. Despite its modest cost and ease of implementation, this approach improves the reliability only to a small extent, which is not desirable, especially for large-scale systems. In this paper, we propose a new approach to improve reliability of the networks, called reducing nodes. Extensive reliability analyses from two major perspectives, terminal and broadcast, demonstrate that this idea can achieve a tremendous advantage over the aforementioned approach.

Scalable crossbar network: a non-blocking interconnection network for large-scale systems

Interconnection networks (INs) are used in wide applications of multi-processor systems in order to set up connections between various nodes such as processors and memory modules. However, there is a fundamental problem in INs that has always been considered as one of the most challenging issues in this area. Blocking problem in these networks degrades network performance and consequently the performance of the whole system. In the meantime, the main option for dealing with this problem is the use of non-blocking crossbar networks. However, there are engineering and scaling difficulties when using these networks in large-scale systems. The number of pins on a VLSI chip cannot exceed a few hundreds, which restricts the size of the largest crossbar that should be integrated into a single VLSI chip. Using the idea of multistage implementation of crossbar network can resolve the problem. However, the next problem that arises with this idea is high hardware cost. Therefore, in this paper, a new implementation of crossbar network named scalable crossbar network (SCN) that is a non-blocking network is presented to cope with the aforementioned scaling problems. In addition, performance analysis results show that SCN outperforms multistage crossbar networks and multistage interconnection networks in terms of terminal reliability, mean time to failure, and system failure rate.

Emulation of multistage interconnection networks by fibre memory

A ‘fibre-switch block’ is a switch with delay lines that feedback from some outputs to inputs. In every unit time, it receives and transmits a packet concurrently. A ‘fibre memory’ means a multi-block serial connection. Its performance of time-multiplexed operation is often said to ‘emulate’ a multistage interconnection network. This study formulates this concept of emulation. The formalised concept is useful in the design and validation of various switching functionalities, including timeslot interchanging, sorting, merging and concentration. For illustration, ‘banyan-type networks’, ‘Clos network’ and several familiar multi-stage sorting networks are all efficiently emulated.

Bidirectional Data Vortex Optical Interconnection Network: BER Performance by Hardware Simulation and Evaluation of Terminal Reliability

In this paper, we present bi-directional data vortex interconnection network in which the packets are routed both in the forward as well as in the reverse directions. We have simulated the hardware model of a single node with data flow from the node in both the directions and routing. The cascading performance of nodes has been studied by varying the input power from −15 to 0 dBm and BER characteristics up to 70 cascaded nodes have been verified. The terminal reliability analysis of bi-directional data vortex is carried out, as reliability and fault tolerance are important parameters for any multistage interconnection network. Finally, the comparison of the terminal reliability between the proposed bidirectional architecture with two data vortex networks connected in parallel for bidirectional operation is presented.

On Performance Evaluation of Advance Irregular Alpha Multi-Stage Interconnection Network-2

In this paper, the author has proposed a new multi-stage interconnection network named as advance irregular alpha multi-stage interconnection network-2 (AIAMIN-2). The AIAMIN-2 is a single switch fault tolerant network. It is compared with modified alpha network (MALN) and irregular modified augmented baseline network (IMABN). Results show that AIAMIN-2 performs better than the MALN and IMABN in faulty and non-faulty conditions.

Pars network: A multistage interconnection network with fault-tolerance capability

Interconnection networks are used for communication between nodes in multi-processor systems as well as super-systems. These systems require effective communication between the processor and memory blocks and therefore, interconnection networks are considered as the heart of the parallel processing and multi-processor systems. Multistage interconnection networks (MINs) are the main option for use in supercomputer environments that consist of thousands of processing elements. In this paper, a regular class of fault-tolerant MINs named Pars network along with its routing algorithm are presented. Analytical results demonstrate that the Pars network outperforms known regular networks, namely ABN, ASEN, EGN, and IEGN in terms of cost, fault-tolerance, terminal reliability, mean time to failure, and permutation capability.

Analyzing the reliability of shuffle-exchange networks using reliability block diagrams

Supercomputers and multi-processor systems are comprised of thousands of processors that need to communicate in an efficient way. One reasonable solution would be the utilization of multistage interconnection networks (MINs), where the challenge is to analyze the reliability of such networks. One of the methods to increase the reliability and fault-tolerance of the MINs is use of various switching stages. Therefore, recently, the reliability of one of the most common MINs namely shuffle-exchange network (SEN) has been evaluated through the investigation on the impact of increasing the number of switching stage. Also, it is concluded that the reliability of SEN with one additional stage (SEN+) is better than SEN or SEN with two additional stages (SEN+2), even so, the reliability of SEN is better compared to SEN with two additional stages (SEN+2). Here we re-evaluate the reliability of these networks where the results of the terminal, broadcast, and network reliability analysis demonstrate that SEN+ and SEN+2 continuously outperform SEN and are very alike in terms of reliability.

Reliability Evaluation and Routing Integration in Shuffle Exchange Omega Network

Multistage Interconnection Networks (MINs) are design to provide an effective communication in switching. Shuffle-exchange networks (SENs) have been widely considered as practical interconnection systems due to their size of it switching elements (SEs) and uncomplicated configuration. In this paper, the relationship between reliability performance and number of network size are compared in shuffle exchange network (SEN) and SEN with minus one stages (SEN-). There are three parameters used to measure the reliability performance on these networks which is terminal reliability, broadcast reliability and network reliability. An addition this paper also focused on comparing the algorithm based on SEN- to achieve the optimal routing time and the number of passes. The algorithms consist of six algorithms namely ZeroX, ZeroY, ZeroXbit, ZeroYbit, Sequential Increasing and Sequential Decreasing algorithm. This paper also shows the details of the illustrative examples used to explain each parameter measures. At the end of this chapter, the comparative analysis shows the performance of each parameters measures.

Design of 4-disjoint gamma interconnection network layouts and reliability analysis of gamma interconnection Networks

Multistage interconnection networks (MINs) are widely used for reliable data communication in a tightly coupled large-scale multiprocessor system. High reliability of MINs can be achieved using fault tolerance techniques. The fault tolerance is generally achieved by disjoint paths available through multiple connectivity options. The gamma interconnection network (GIN) is a class of fault tolerant MINs providing alternate paths for source---destination node pairs. Various 2-disjoint and 3-disjoint GIN architectures have been presented in the literature. In this paper, two new designs of 4-disjoint paths multistage interconnection networks, called 4-disjoint gamma interconnection networks (4DGIN-1 and 4DGIN-2) are proposed. The proposed 4DGINs provide four disjoint paths for each source---destination pair and can tolerate three switches/link failures in intermediate interconnection layers. Proposed designs are highly reliable GIN with higher fault-tolerant capability than other gamma networks at low cost. Terminal pair reliabilities of proposed designs and various other 2-disjoint and 3-disjoint GINs are evaluated, analyzed and compared. Reliability values of proposed designs are found higher.

Improved extra group network: a new fault-tolerant multistage interconnection network

Supersystems are shown to provide enough computational power to solve complex problems on a real-time basis. In all these systems, the computational parallelism is obtained from multiple processors. Multistage interconnection networks (MINs) play a vital role on the performance of these multiprocessor systems. This paper introduces a new fault-tolerant MIN named as improved extra group network (IEGN). IEGN is designed by existing extra group (EGN) network, which is a regular multipath network with limited fault tolerance. IEGN provides four times more paths between any source---destination pairs compared with EGN. The performance of IEGN has been evaluated in terms of permutation capability, fault tolerance, reliability, path length, and cost. It has also been proved that the IEGN can achieve better results in terms of fault tolerance, reliability, path length and cost-effectiveness, in comparison to known networks, namely, EGN, augmented baseline network, augmented shuffle-exchange network, fault-tolerant double tree, Benes network, and Replicated MIN.

A GreedyZero algorithm to minimise the conflicts in an Optical Multistage Interconnection Network

An Optical Multistage Interconnection Network (OMIN) is an important class of Interconnection Network that has large transmission capacity in the communication networks. One of the severe problems is the conflict which is caused through coupling two signals within switching elements. In this paper, we have proposed a new algorithm to minimise the number of conflicts of OMINs using the greedy graph colouring and Zero algorithm. The greedy graph colouring approach employed the Zero algorithm to categorise inputs of the OMINs without conflict. The results showed that the number of passes reduced by approximately 30%. In addition, the average execution time of our proposed algorithm was less than the average execution time of the Zero algorithm.

Application of t-shuffle permutation matrices in delta interconnection networks

We define some important properties of the permutation matrices of t-shuffle type which can be used to synthesize omega and inverse omega multistage interconnection networks. We also address some features of these networks compared to other networks of delta type. Finally, we propose one modification of omega network which decreases the number of stages in the network.

Performance Tuning of Dual-priority Delta Networks through Queuing Scheduling Disciplines

Differentiated Services (DiffServ) and other scheduling strategies are now widespread in the traditional, “best effort” Internet. These Internet Architectures offer Quality of Service (QoS) guarantees for important customers at the same time as supporting less critical applications of lower priority. Strict priority queuing (PQ), weighted round robin (WRR), and class-based weighted fair queuing (CBWFQ) are three common scheduling disciplines for differentiation of services in telecommunication networks. In this paper, a comparative performance study of the above PQ, WRR and CBWFQ queuing scheduling policies applied on a double-buffered, 6-stage Multistage Interconnection Network (MIN) that natively supports a 2-class priority mechanism is presented and analyzed using simulation experiments. We also consider a 10-stage MIN, to validate that the conclusions drawn from the 6-stage MIN apply to MINs of different sizes. The findings of this paper can be used by MIN designers to optimally configure their networks.

An Effective and Feasible Congestion Management Technique for High-Performance MINs with Tag-Based Distributed Routing

As parallel computing systems increase in size, the interconnection network is becoming a critical subsystem. The current trend in network design is to use as few components as possible to interconnect the end nodes, thereby reducing cost and power consumption. However, this increases the probability of congestion appearing in the network. As congestion may severely degrade network performance, the use of a congestion management mechanism is becoming mandatory in modern interconnects. One of the most cost-effective proposals to deal with the problems derived from congestion situations is the Regional Explicit Congestion Notification (RECN) strategy, based on using special queues to totally isolate the packet flows which contribute to congestion, thereby preventing the Head-of-Line (HoL) blocking effect that these flows may cause to others. Unfortunately, RECN requires the use of source-based routing, thus not being suitable for interconnects with distributed routing, like InfiniBand. Although some RECN-like mechanisms have been proposed for distributed-routing networks, they are not scalable due to the huge amount of control memory that they require in medium-size or large networks. In this paper, we propose Distributed-Routing-Based Congestion Management (DRBCM), a new scalable technique which, following the RECN principles, totally prevents congestion from producing HoL-blocking in multistage interconnection networks (MINs) using tag-based distributed routing. Simulation results indicate that, regardless of network size, DRBCM presents small resource requirements to keep network performance at maximum level even in scenarios of heavy congestion, where it utterly outperforms (with a gain up to 70 percent) current solutions for distributed-routing networks, like the InfiniBand congestion-control mechanism based on injection throttling. Thus, DRBCM is an efficient, cost-effective, and scalable solution for congestion management.

Improved Meta-Flattened Butterfly Multistage Interconnection Network

processing is efficient form of information processing which means to implement high performance computing systems. A communication network that links processors and memory modules determines the efficiency of these parallel systems. To provide the required connectivity and performance at reasonable cost, an interconnection network is used. Hence, multistage interconnection networks are a good way for providing communication in these systems. This paper includes two major contributions. Firstly, it describes the flaws of existing Meta- flattened Network (MFN). Secondly, a new Fault-tolerant multistage interconnection network named as Improved Meta- Flattened Butterfly Network (IMFN) is proposed that can improve the routing problems of Meta-flattened Network. Performance of the proposed network is analyzed in terms of cost and permutation possibility. The performance comparison of the IMFN with MFN shows that the proposed network IMFN gives much better performance in terms of permutation.

On the Minimization of Crosstalk Conflicts in a Destination Based Modified Omega Network

In a parallel processing system, Multi-stage Interconnection Networks (MINs) play a vital role in making the network reliable and cost effective. The MIN is an important piece of architecture for a multiprocessor system, and it has a good impact in the field of communication. Optical Multi-stage Interconnection Networks (OMINs) are the advanced version of MINs. The main problem with OMINs is crosstalk. This paper, presents the (1) Destination Based Modified Omega Network (DBMON) and the (2) Destination Based Scheduling Algorithm (DBSA). DBSA does the scheduling for a source and their corresponding destination address for messages transmission and these scheduled addresses are passed through DBMON. Furthermore, the performance of DBMON is compared with the Crosstalk-Free Modified Omega Network (CFMON). CFMON also minimizes the crosstalk in a minimum number of passes. Results show that DBMON is better than CFMON in terms of the average number of passes and execution time. DBSA can transmit all the messages in only two passes from any source to any destination, through DBMON and without crosstalk. This network is the modified form of the original omega network. Crosstalk minimization is the main objective of the proposed algorithm and proposed network.

Evaluation of Two Terminal Reliability of Fault-tolerant Multistage Interconnection Networks

This paper iOntroduces a new method based on multi-decomposition for predicting the two terminal reliability of fault-tolerant multistage interconnection networks. The method is well supported by an efficient algorithm which runs polynomially. The method is well illustrated by taking a network consists of eight nodes and twelve links as an example. The proposed method is found to be simple, general and efficient and thus is as such applicable to all types of fault-tolerant multistage interconnection networks. The results show this method provides a greater accurate probability when applied on fault-tolerant multistage interconnection networks. Reliability of two important MINs are evaluated by using the proposed method.

A Universal Stabilization Algorithm for Multicast Flows with Network Coding

In this paper, we consider a network that supports multiple multicast flows with network coding. It is well-known that network coding can be used to increase the throughput of a delay-free network. However, as there are multiple multicast flows in the network, packets might be delayed due to contention. As packets from the same flow have to be synchronized for network coding, additional buffers, known as em synchronization buffers in the literature, are required. In certain networks, such as multistage interconnection networks in switch fabrics , the size of internal buffers could be quite limited. One of the key contributions of the paper is to propose a packet scheduling algorithm so that synchronization buffers can be bounded by a em finite constant that only depends on the maximum hop count of the flows. We also show that our scheduling algorithm does not cause any throughput degradation as it can stabilize the network for any em admissible traffic. Moreover, our algorithm is em universal and it does not require to know the rates of the flows in the network. The main idea of our algorithm is to introduce em fictitious packets in the dynamic frame sizing algorithm recently proposed in for stabilizing switches and em wired networks (without network coding). By so doing, packets that might be stalled in synchronization buffers can be flushed out. We show that the number of fictitious packets in each frame is also bounded by a finite constant that only depends on the maximum hop count.

A Cost-Effective Architecture For Optical Multistage Interconnection Network

In this paper a new architecture for Optical Multistage Interconnection Networks (OMINs) has been proposed to avoid crosstalk problem. At the same time, the probablity of losing pass through an optical long connection path is reduced in this architecture. The new architecture is inherent form the standard OMIN by converting two switches of the network to one switch in each row. By reducing the number of switches in new architecture, the reduction in the execution time is considered. The modifying in the number of passes via the same low stage transformation is negligible. The ability of the new architecture to decrease cost and avoid crosstalk has been validated through simulations that show improvement in the network performance in terms of approximately 30% reduction in the execution time.

Optical interconnection reverse data vortex network: performance analysis

Multistage interconnection networks are employed in data centres to interchange information between the processors and memory elements. Data Vortex (DV) is a multistage minimum logic network which can be used in data centres. DV satisfies the requirements of the interconnection networks such as scalability and throughput. However, the latency is on higher side, and reduction in latency can lead to higher throughput. In the present paper, we describe the feasibility and performance analysis of DV architecture in reverse direction. The routing and the possible hardware model of the node switch have been discussed. We present the performance analysis of Reverse Data Vortex (RDV) architecture in terms of throughput, latency and latency distribution. A comparative study with DV on throughput, latency and latency distribution is also presented. The simulation result shows that the decrease in latency of RDV is about 50 % that of DV and this leads to an increase in injection rate of RDV to values more than two times that of DV.