Multistage Interconnection Networks Research Articles

A Survey of Multistage Interconnection Networks

Background: Multistage interconnection networks are being used in computer and communications. Multiprocessor architectures for parallel computing exercise these interconnection networks for connecting various processing elements and transfer data between sub-systems of a digital system. The vast diversity of the field poses an obstacle to realize different kinds of interconnection networks and their relationship. Methods: This paper consists of an extensive survey of multistage interconnection networks. Results: A broad classification of multistage interconnection networks based on network functionality, reliability and fault tolerance is presented in order to emphasize the important principles which differentiate the network architectures. For each class of network, significant results are given and the basic design principles are explained. Conclusion: The various multistage interconnection networks design provide high performance, availability, throughput, lower latency, less power consumption along with improved fault-tolerance and reliability. However, there is a rising demand for new fault-tolerant and reliable multistage interconnection networks.

Parallel SEN: a new approach to improve the reliability of shuffle-exchange network

In the past few decades, the demand for high-performance computing has been increasingly growing. These systems usually employ many processing elements working together via interconnection networks to solve complicated problems. Due to the efficiency and cost productivity, multistage interconnection networks (MINs) are recommended for use in such systems. At the same time, shuffle-exchange networks (SENs) have extensively been used as a suitable solution to multistage interconnection networks, given the size of their switching elements and simple configurations. In this paper, parallel SEN (PSEN) is proposed to enhance the reliability of these networks. Moreover, PSENs with one and two more stages (PSEN+ and PSEN+2) are utilized to optimize the reliability factor. The reliability analysis of the proposed network is performed through the reliability block diagram. According to the evaluation results, PSEN achieved higher reliability compared to SEN in different aspects of reliability, such as terminal, broadcast, and network. The proposed network also improves the cost-effectiveness in comparison with other MINs.

Design of an Efficient N × N Butterfly Switching Network in Quantum-Dot Cellular Automata (QCA)

Quantum-dot cellular automata (QCA) is a rapidly growing nanotechnology very well suited for designing ultra-dense, low-power, and high-performance digital circuits. In parallel computing, the multistage interconnection network (MIN) provides maximum bandwidth to the components and minimum latency access to the memory modules. Much research has been conducted on CMOS-based MINs for parallel computing. However, the QCA-based switching network is still underexplored. This article proposes a QCA architecture of a new single-layer butterfly switching network (BSN). To achieve this, we design an efficient 2 × 2 switching element (SE), using a modified majority ( $\mathcal{M}{_{[x,y]}}$ ) gate that is fully utilized (i.e., no fixed logic like “0” and “1” at the inputs). The use of a fully utilized majority gate over a partially utilized majority (PUM) one makes the proposed SE more cost-efficient and versatile, and therefore it is used as the building block for designing the switching network. In addition, we deploy the SE to realize 4 × 4 and 8 × 8 BSNs. We also show how the design can be extended for an N × N BSN. All the proposed circuits have been modeled and verified by QCADesigner. QCAPro is used for estimating the average switching and leakage energy dissipation of the proposed circuits. The results show considerable enhancement in terms of cell count, device area, and latency, and thereby outperform all reported prior designs.

Impact of Raising Switching Stages on the Reliability of Interconnection Networks

Multistage Interconnection Networks (MINs) are a cost-effective idea for connection between different nodes in multi-processor systems. In the meantime, understanding the impact of increasing the number of stages (i.e. a famous method for improving fault tolerance) on the reliability of these networks is essential. Last studies on this challenging issue, revealed that adding one switching stage to MINs is preferable to two in terms of reliability. However, there were some non-negligible gaps in previous researches: (i) The probability of failure for terminal nodes was not considered in the calculation of reliability. (ii) Numerical results were only based on the small size of the network, i.e. 8 × 8. (iii) Reliability analyses were time-independent. (iv) The lack of some important parameters such as the mean time to failure and availability was noticeable. Therefore, this paper will take a more comprehensive analysis of reliability to meet the above specifications.

On Topological Indices for Swapped Networks Modeled by Optical Transpose Interconnection System

The optical transpose interconnection system (OTIS) network has many application in architecture for parallel as well as in distributed network. The optical translate interconnection system utilizes a straightforward pair of lenslet clusters to execute a coordinated interconnection that is valuable for mix based multistage interconnection networks, work of-trees network processors, and hypercubes. In Cancan (2019) and Hayat et al. (2014), different interconnection network has studied related to topological indices. In this article we have computed the Ve-degree and Ev-degree base topological indices of swapped network by taking path and complete graph as original graphs. We have included some dedicated formulas for different types of topological indices for the OTIS swapped network by taking the path and complete graph on n vertices as basis of graph.

Terminal reliability analysis of multistage interconnection networks

Terminal reliability of multistage interconnection network (MIN) is the probability of at least one fault free path between any source–destination nodes pair. MIN is used to interconnect processors and memory modules in multi-processor system. In this paper, terminal reliability is estimated and validated for existing MINs (i.e., SEN, SEN+, SEN+2, GIN, CGIN, PCGIN, 3D-GIN, 4D-GIN-1, 4D-GIN-2, 4D-GIN-3, and SEGINs). The comparison and performance analysis of MINs based on various indices are also presented.

Multi-stage Interconnection networks CLOS/BENES Parallel Routing Algorithms for circuit switching system

This article approaches the design of parallel routing Clos and Benes switching networks in Communication Technology. In communication, the transmission of data with less traffic and low latency are the biggest challenges. The conventional packet switching circuits takes the more power and high area to overcome this problem parallel routing algorithms are proposed. Clos and Benes networks are designed for the circuit switching systems where the switching configuration will be rearranged and it’s relatively low speed. Most of the existing parallel routing algorithms are not practical those are fail to interconnects the inputs with the matched outputs with less traffic. In this article, we designed Clos and Benes network. Clos and Benes networks are the Non-blocking switching Networks. Clos Switching network provides the better results like low area and less delay when compare with the Benes Switching Network. Clos and Benes non-blocking switching circuits are designed by Verilog HDL, Synthesized and simulated by XILINX 12.1 tool

Design and Implementation of Rearrangable Non-Blocking Switching Network in VLSI

The main goal of this article is to implement an effective Non-Blocking Benes switching Network. Benes Switching Network is designed with the uncomplicated switch modules & it’s have so many advantages, small latency, less traffic and it’s required number of switch modules. Clos and Benes networks are play a key role in the class of multistage interconnection network because of their extensibility and mortality. Benes network provides a low latency when compare with the other networks. 8x8 Benes non blocking switching network is designed and synthesized with the using of Xilinx tool 12.1.

Mean Time to Failure Analysis in Shuffle Exchange Systems

Multistage Interconnection Network (MIN) has been researched for the interconnection implementation of switches and multiprocessors. The topology of the interconnection, the number of stage and the switching element used in the network distinguish between each MIN's tolerance of failure.This paper introduces a topology called Replicated Shuffle Exchange Network and Replicated Augmented Shuffle Exchange Network. A replicated technique is described for making the network more reliable. The replicated technique results in reduced the Mean Time to Failure in the network. Performance measurement shows that replicated network achieve a significant improvement over a basic network have been measured.

Enhancement Replicated Network: A Reliable Multistage Interconnection Network Topology

Shuffle-exchange networks (SENs) have been generally considered to provide convenient interconnection systems due to the size of their switching elements and simple configuration. Notwithstanding the evaluation of the reliability performance of SENs attempted by researchers in the past, this paper provides an in-depth study. This paper proposes a new topology called the Replicated Enhanced Augmented SEN. This topology makes use of an Enhanced Augmented SEN by replicating the network to create a redundant path and increase the reliability performance. The reliable operation of interconnection networks is the main concern in system performance. Reliable operation in multistage interconnection networks depends on their topology, network configuration, and number of stages in the system. The terminal reliability analysis showed that the approach of using a replicated network resulted in the highest performance in terms of reliability.

Reliability study of U-type multistage interconnection networks

Multistage Interconnection Networks (MINs) are used in wide applications of multiprocessor systems in order to set up connections between various nodes such as processors and memory modules. Reliability can be considered as one of the most challenging issues in these systems because this can degrade or cancel the network performance and consequently the effort of the whole system. Here, a type of multistage fabric called U-type is selected for study, particularly in terms of its reliability. This fabric turns out to be the most appropriate type for constructing parallel systems due to the particular features that it possesses. This study reveals that U-type fabrics are ideal devices as they present mostly high values of reliability and low values of latency compared to unidirectional fabrics. This behaviour becomes more intensive when it is used in a cluster that demands service that includes a high percentage of “local type traffic.” Thus, U-type multistage devices can considerably enhance the connection points in constructing parallel systems, improving internal data flows.

Design and reliability analysis of fault-tolerant shuffle exchange gamma logical neighborhood interconnection network

Multistage interconnection networks are used as a medium for interconnecting processors and memories in multiprocessor systems. Multistage interconnection networks are an effective substitute for crossbar switches, used in telephone network systems and parallel computers, due to their low cost, better performance and easy maintainability. In this paper, we propose new fault-tolerant hybrid multistage interconnection networks obtained from shuffle exchange gamma interconnection network (SEGIN) and logical neighborhood network named as shuffle exchange gamma logical neighborhood interconnection network (SEGLNIN). We evaluated the performance of SEGLNIN in terms of disjoint paths, reliability and hardware cost and compared it with some well-known MINs like shuffle exchange network (SEN), shuffle exchange network with one extra stage (SEN +) and shuffle exchange network with two extra stages (SEN + 2), SEGIN-1, and SEGIN-2. The results illustrate that the performance of the proposed SEGLNIN is better than that of the compared networks in terms of reliability and disjoint paths.

Design and Reliability Evaluation of Gamma-Minus Interconnection Network

Gamma Interconnection Network (GIN) is characterized as Redundant Multistage Interconnection Network (MIN) which is considered as a potential candidate for use in broadband communications. Several advancements have been made to improve Reliability indices such as Terminal Reliability (TR), Broadcast Reliability (BR) and Network Reliability (NR) of these networks. But inspite of these advancements, there are certain issues which are yet to be explored such as Complexity, Cost, Number of disjoint paths on presumption that source/destination are failure free. Most of the work done in the literature addresses TR only and less work has been done on analysis of BR and NR. In literature networks, [Formula: see text] size has been explored and no attention has been paid to bigger network sizes although reliability of bigger size network is important for parallel processing systems. In this paper, existing class of Gamma Networks has been studied extensively and modifications have been proposed in existing Gamma Network which minimizes or resolves most of the limitations mentioned above. The proposed Gamma-Minus Network has more redundant paths than other networks. Proposed Network has been compared with some recently introduced members of this class. The results show that newly proposed Gamma-Minus Network has better reliability with lowest cost and path length and provides disjoint minimal-path set for [Formula: see text] to [Formula: see text] network size. The routing used in this paper eliminates the backtracking overhead which minimizes transmission delay.

A review on gamma interconnection network

Multistage interconnection networks (MIN) are widely used in super computer systems for reliable communication, because of their cost effectiveness, fault tolerance property and low transmission delay. Researchers have compared various MIN on basis of their reliability and fault tolerance but the selection of MIN was random. In this paper all MIN belongs to gamma class of networks proposed yet are compared on various reliability issues. Also, in literature same value for reliability has been taken for different sizes of SE, wherein here in this paper different reliability values have been applied to different type of SE to compute reliabilities. Terminal reliability of these networks have been computed and compared for all possible tag values for network size of 8 × 8,while as in other research works TR has been calculated for tag value = '0' only.

Effect of Different Connection Patterns of MUX and DEMUX on Terminal Reliability and Routing Scheme of Gamma-Minus MIN

In parallel and distributed systems, multistage interconnection network (MIN) plays an important role for its efficient communication between processor and memory at a very low cost. A major class of MIN called Gamma network is known for its redundant network topology and is being used in broadband communication systems. The increased redundancy incorporation makes these networks more complex and hence reliability evaluation becomes complex. The performance evaluation of these network topologies requires reliability evaluation utilizing routing mechanism or techniques. In this paper, we have proposed four topologies of Gamma-Minus network using MUX and DEMUX. Terminal Reliability (TR), fault tolerance and routing schemes of Gamma-Minus network topologies proposed have been computed by utilizing different connection patterns of MUX/DEMUX. Also, performance indices such as TR, Reliability Cost Ratio (RCR), Fault Tolerance, etc. computed for different Gamma-Minus architectures have been compared with the existing Gamma networks, other than Gamma-Minus. All the performance indices for different Gamma-Minus topologies show improvement over the performance indices of different Gamma networks. The proposed Gamma-Minus architectures have been compared among themselves and also Gamma-Minus2 shows the best performance for all performance indices. To the best of our knowledge, most of the researchers have not compared fault tolerance and RCR performance measure.

Nonblocking Multirate 2-Stage Networks

A 2-stage network is the most compact multistage interconnection network (MIN) for interconnecting small switches to form a large one. For larger networks, the switches in each stage can be replaced with 2-stage networks to reduce crosspoint cost. The 2-stage network preserves only conditional nonblockingness, while a multirate 2-stage network preserves nonblockingness. Multirate MINs have been exploited in many prior works, but multirate 2-stage networks have not previously been studied. In this letter, we prove the necessary and sufficient conditions for strictly nonblocking, rearrangeable nonblocking, and re-packable nonblocking multirate 2-stage networks. The results can be directly applied to the architecture design of elastic optical networks which allocate a flexible use of the spectrum to each connection, as each space switch is replaced with a bandwidth-variable waveband-converting switch, which has full-range conversion capability.

Number of Stage Implication Towards Multistage Interconnection Network Reliability

Number of Stage Implication Towards Multistage Interconnection Network Reliability

Rearranging links: a cost-effective approach to improve the reliability of multistage interconnection networks

The use of multiprocessor systems is the main method for providing a high computational power. Multistage interconnection networks (MINs) are widely used to connect processors and memory modules in multiprocessor systems. Therefore, the design of an efficient MIN is an essential requirement for the development of multiprocessor systems. In addition, a critical parameter for any efficient interconnection network is reliability. However, the problem in the way of designing high-reliable interconnection networks is high hardware cost. To solve this problem, contribution of this paper is to propose a new approach to improve the reliability of the MINs, called the rearranging links. The proposed approach is implemented on two common MINs namely extra-stage shuffle-exchange network (SEN+) and augmented shuffle-exchange network (ASEN). Meticulous analysis of terminal reliability proves that the proposed approach is an efficient method to improve the reliability of MINs. In addition, performed cost analysis confirms that utilising it leads to emerge cost-effective MINs.

Rearranging links: a cost-effective approach to improve the reliability of multistage interconnection networks

Rearranging links: a cost-effective approach to improve the reliability of multistage interconnection networks

An Efficient Parallel Algorithm for Latin Square Design: A Multi Core CPU Approach

Abstract— The theory of Latin squares is very important tool in design theory. Like much of design theory, Latin squares have various applications in statistics, finite geometries and experimental design, to name a few. In this paper, we proposed an efficient parallel algorithm for Latin square design which have desirable properties for parallel array access. These squares provide conflict free access to various subsets of an n x n array using n memory modules. A transversal of such a square is a set of n entries such that no two entries share the same row, column or symbol. We present a general construction method for building parallel Latin square of order n2 for all n.
 The proposed algorithm presents a quick parallel method to produce a Latin square design and a parallel conflict access of data in SIMD system. The simulation results of the proposed parallel algorithm for Latin square design were compared with the traditional sequential algorithm Latin square design in terms of speedup and efficiency. The results of parallel Latin Square design were very promising and showed a potential that this design could successfully be applied to the parallel routing problems for conflict free data access. At last, the results show that the parallel versions of former sequential algorithm with simple modifications achieve the super linear speedup up to 200 times for matrix size of 256.
 
 Index Terms: Latin square, multi core processor, parallel processing, simulation, parallel memory system, skewing scheme, multistage interconnection network.