Design and Implementation of Multistage Interconnection Networks for SoC Networks

Abstract

In this paper the focus is on a family of Interconnection Networks (INs) known as Multistage Interconnection Networks (MINs). When it is exploited in Network-on-Chip (NoC) architecture designs, smaller circuit area, lower power consumption, less junctions and broader bandwidth can be achieved. Each MIN can be considered as an alternative for an NoC architecture design for its simple topology and easy scalability with low degree. This paper includes two major contributions. First, it compares the performance of seven prominent MINs (i.e. Omega, Butterfly, Flattened Butterfly, Flattened Baseline, Generalized Cube, Benes and Clos networks) based on 45nm-CMOS technology and under different types of Synthetic and Trace-driven workloads. Second, a network called Meta-Flattened Network (MFN), was introduced that can decrease the blocking probability by means of reduction the number of hops and increase the intermediate paths between stages. This is also led into significant decrease in power consumption.