On Asymptotic Analysis of Packet and Wormhole Switched Routing Algorithm for Application‐Specific Networks‐on‐Chip

Nitin Nitin

doi:10.1155/2012/216406

Abstract

The application of the multistage interconnection networks (MINs) in systems‐on‐chip (SoC) and networks‐on‐chip (NoC) is hottest since year 2002. Nevertheless, nobody used them practically for parallel communication. However, to overcome all the previous problems, a new method is proposed that uses MIN to provide intra‐(global) communication among application‐specific NoCs in networks‐in‐package (NiP). For this, four O(n)2 fault‐tolerant parallel algorithms are proposed. It allows different NoCs to communicate in parallel using either fault‐tolerant irregular Penta multistage interconnection network (PNN) or fault‐tolerant regular Hexa multistage interconnection network (HXN). These two are acting as an interconnects‐on‐chip (IoC) in NiP. Both IoC use packet switching and wormhole switching to route packets from source NoC to destination NoC. The results are compared in terms of packet losses and wormhole switching which comes out to be better than packet switching. The comparison of IoC on cost and MTTR concluded that the HXN has the higher cost than the PNN, but MTTR values of the HXN are low in comparison to the PNN. This signifies that the ability to tolerate faults and online repairing of the HXN is higher and faster than the PNN.

Highlights

Introduction and MotivationParallel Processing refers to the concept of speeding-up the execution of a program by dividing the program into multiple fragments that can execute simultaneously, each on its own processor
It allows different NoCs to communicate in parallel using either fault-tolerant irregular Penta multistage interconnection network (PNN) or fault-tolerant regular Hexa multistage interconnection network (HXN)
It is depicted that the cost of the HXN is higher in comparison to the PNN

Summary

Introduction and Motivation

Parallel Processing refers to the concept of speeding-up the execution of a program by dividing the program into multiple fragments that can execute simultaneously, each on its own processor. Several forces drive the adoption of NoC architecture: from a physical design viewpoint, in nanometer Complementary Metal-Oxide Semiconductor (CMOS) technology interconnects dominate both performance and dynamic power dissipation, as signal propagation in wires across the chip requires multiple clock cycles. The said architecture uses O(n) time fault-tolerant packet and wormhole switching parallel algorithms These algorithms allow different NoCs to communicate efficiently in parallel with. The rest of the paper is organized as follows: Section 2 describes the general NiP architecture including the faulttolerant parallel algorithm designed to provide parallel communication among different NoCs using HXN and PNN followed by the their comparisons on Cost and Mean Time to Repair (MTTR).

Application-Specific NiP Architecture Using Irregular PNN and Regular HXN

Fault-Tolerant Dynamic Switching Algorithms

Reached successfully

Results and Discussions

Conclusion