Multiple-gate FETs Research Articles

Fin Cross-Section Shape Influence on Short Channel Effects of MuGFETs

Multiple-gate FETs is normally constructed on pre-etched silicon fins. These devices often present casual width variations along the silicon height; mostly caused by technological limitations of the fin definition process, due to non-ideal anisotropic etch. The resulting devices have, consequently, non-rectangular cross-sections, which can affect their electrical behavior. This work addresses the dependence of fin width non-uniformity on the occurrence of short-channel effects through comparative analysis, based on threedimensional numeric simulation of non-rectangular cross-section devices. The influence of the fin crosssection shape on electrical parameters showed to be dependent on channel length, becoming more sensible to the fin shape as the channel length is reduced, with better DC performance present on devices with bottom fin width smaller than top fin width due to the higher transconductance and lower output conductance, resulting on higher intrinsic voltage gain. For opposite fin shapes the total gate capacitance present higher values, beneficiating AC analog parameters, such as unit gain frequency.

Unified compact model for junctionless multiple-gate FETs including source/drain extension regions

This paper presents a unified compact model for a junctionless (JL) multiple-gate (MG) FET operating in the subthreshold region. A unified center potential model for double-gate, triple-gate, and quadruple-gate (QG) JL FETs is obtained using a quasi-3D scaling equation. The source/drain (S/D) extension regions are also modeled depending on the S/D extension length. The subthreshold current and subthreshold characteristics such as the subthreshold slope, threshold voltage, and drain-induced barrier lowering are analytically modeled for JL MG FETs. Comparison of the proposed models with numerical simulation results obtained using Sentaurus TCAD showed good accuracy, even for a very-short-channel QG device with a channel length of 10 nm. The proposed compact model can be used for low power circuit applications of JL MG FETs.

Strained p-Channel MOSFET Fabrication Challenge and Perspective for the 28-Nm Technology Node and Beyond

Carrier mobility enhancement technique was introduced to ULSI manufacture since 90-nm technology node. As one of promising mobility enhancement techniques, the strain/stress at the channel region of metal-oxide-semiconductor field effect transistors (MOSFETs) modulates the lattice constant and band structure of silicon then enhances the hole/electron mobility. [1] The high mobility gives high source injection velocity into the quasi-ballistic transport channel which can provide high drive current and high circuit speed of MOSFETs. [2] Among a great variety of mobility enhancement techniques by applying stress to induce appropriate strain in the p-channel region, forming embedded epitaxial Si1-xGex with recessed Source/Drain (S/D) structure has been reported as one powerful technique. [3] The Sigma-shaped silicon recess profile is applied before epitaxial Si1-xGexgrowth, because the strain force on the channel of MOSFET is increased effectively by narrowing spacing between source and drain. [4] In this manuscript, we utilized one-step and two-step dry etch process with the same alkaline solution wet etch to form Sigma-shaped silicon recess profile for the planar p-channel MOSFETs. After comparing the recess depth loading correlated to the pitch of gate electrodes (Table 1), we also studied the tunable capability and limitations on tip depth, tip proximity and total depth of Sigma-shaped trench for these two different dry etch processes. The strict profile control of Sigma-shaped profile is not only led by the device performance variation demand but also needed to get the excellent epitaxial Si1-xGex crystallinity. Besides that, Si-C bond on the trench surface could inhibit the epitaxial Si1-xGex growth, thus resulting in defects on S/D area. We proved that high H2 volume ash process could effectively remove the Si-C bond at trench surface and greatly reduce the Si1-xGexdefect counts. (Fig. 1) Recently, the further down-scaling of planar MOSFETs technology is facing a serious physical limitation which results in short-channel effects (SCEs). Multiple-gate FETs or Fin structure FETs are already adopted in the fabrication process for the excellent control of SCEs from 20-nm technology node. Unlike the conventional planar transistor, a significant portion of the drain current is conducted along the fin sidewalls in FinFETs. Therefore, to realize a large mobility enhancement, the strain/stress techniques of FinFETs should be significantly different from embedded Si1-xGex techniques of traditional planar devices. The Pi-shaped Si1-xGex (Π-Si1-xGex) should be induced to encapsulate the silicon on the top and sidewalls of the narrow fins. [5] In this work, the Π-Si1-xGex stressors should be grown on the top and sidewalls of fins in the S/D regions of p-channel FinFETs. However, due to the loading effect of traditional silicon nitride (SIN) spacer etch, the epitaxial Si1-xGex growth could be hindered by the existence of SIN spacer stringer at the sides of the fin in some special pattern density area. To solve this issue, multi-cycle SIN etch process was attempted in the spacer open step. Compared with the conventional etch process, the multi-cycle SIN etch process delivers the excellent control of spacer pull back loading at universal pattern density area. (Fig. 2) In order to protect the SIN capping layer on the gate top corner and clearly remove the SIN spacer at the top area of fins, the gas types, gas ratio and other parameters are carefully optimized in SIN spacer etch process. We successfully decoupled the trade-off line of capping layer protection and the SIN spacer pull back. Additionally, by balancing the isotropic and anisotropic recess parts in the whole process, we demonstrated the recessed fin structure with flat and smooth surface on the top area, which would be benefit for future good crystalline and well controlled Π-Si1-xGexgrowth. (Fig. 3) ACKNOWLEDGMENT This work was partially sponsored by Program of Shanghai Technology Chief Scientist (B type).

MULTIPLE GATE FIELD-EFFECT TRANSISTORS FOR FUTURE CMOS TECHNOLOGIES

This is a review paper on the topic of multiple gate field effect transistors: MuGFETs, or FinFETs, as they are called. First, the motivation behind multiple gate FETs is presented. This is followed by looking at the evolution of FinFET technologies; the main flavors (variants) of Multigate FETs; and their advantages/disadvantages. The physics and technology of these devices is briefly discussed. Results are then presented which show the performance figures of merit of FinFETs, and their strengths and weaknesses. Finally, a perspective on the future of the FinFET technology is presented.

High-resolution electrical and chemical characterization of nm-scale organic and inorganic devices

Almost ever since the advent of the microelectronics adventure, silicon-based MOSFET (metal–oxide–semiconductor field-effect transistor) technology has been largely dominant. However, for a few years now this technology has exhibited some fundamental limitations in tackling the increasingly challenging issues of miniaturization and improvements in processing speed and power consumption. Hence, new inorganic semiconductor materials (Ge, InGaAs, InP, InSb, GaN, GaSb, SiC, etc.) and new architectures (multiple-gate FETs, nanowire T-FETs, etc.) are being progressively introduced. These new materials are mainly introduced due to their increased mobility (to boost the processing speed of the devices), and the new architectures are required to reduce the junction leakage (and hence reduce the power consumption). These architectures are typically three-dimensional, and with the continuous decrease of dimensions, they also represent extremely confined volumes in which statistical and quantum effects start to play an increasing role. The entirely successful application of these new materials and architectures towards realizable technologies is facing some challenges. The most significant one is probably the impact of defects linked to growth processes and to the presence of stress. Indeed, the presence of different semiconductor materials with different lattice dimensions leads to crystalline defects, threading dislocations, and microtwins that affect the diffusion of dopants and the material mobility (due to scattering). When growth is performed in narrow trenches, dislocations are trapped within the confined volume (aspect-ratio trapping) and, theoretically, defect-free layers can be obtained. However, even if an apparently defect-free layer is obtained, the polar nature of the complex compound materials implies that antiphase boundaries can still be formed, which potentially represent important charge and recombination centers. Beyond the standard logic/memory applications there is a very strong increase in “More than Moore” developments targeting energy (photovoltaic, energy storage), imaging (e.g., quantitative medical imaging), sensor/actuators linked to CMOS-base circuitry, biochips, etc. The utilization of graphene in order to process high mobility (both for holes and electrons) field-effect transistors is also being intensively studied. In all these cases, metrology is a challenge, and no universal solution is identifiable. Moreover in many cases it becomes also very difficult to establish a complete assessment of accuracy, precision and spatial resolution due to a lack of appropriate 3-D standards and comparative metrology. The development of high-performance devices (high speed and density, low consumption) is not the only objective of the electronic industry. The need for low-cost devices processed industrially on flexible and light substrates over very large surfaces has led to the emergence of electronic components based on organic semiconductors. The organic materials used nowadays are typically made of single molecules in highly ordered assemblies or of polymeric semiconductors in thin films. In recent years, an extensive set of organic-based prototypes (transistors, sensors, electrochromic devices, biosensors, photodiodes, photovoltaic cells, etc.) have been developed, demonstrating the strong potential of these materials. However, the advent of commercial applications often requires important breakthroughs towards more efficient and stable organic photovoltaic devices. This implies reduced exciton diffusion lengths (and thus more efficient collection) through the fabrication of an entangled mixture of the acceptor–donor layers, the addition of light scattering nanoparticles or metallic nanoparticles (spectrum harvesting through plasmonics) in the active layer or even wavelength convertors based on metal nanoparticles with a dye to shift the wavelengths. Improving the lifetime of organic solar cells requires incorporating optically transparent inorganic barriers in between the polymer films to prevent moisture penetration. Unfortunately, these organic systems represent an even more challenging metrological problem as compared to their inorganic counterparts, as it no longer suffices to determine the atomic and electrical distributions, but one is also faced with the additional, equally important problem to trace, on the nanometer scale, the chemical configuration and the polymeric information. It is therefore important to develop and improve two- and three-dimensional characterization techniques that can be utilized on both organic and inorganic semiconductors. These techniques should allow determination of the carrier/dopant distribution with an excellent sensitivity and repeatability (within 3 to 5%) with nanometer spatial resolution (subnanometer in inorganic and below 10 nm in organic) over a broad dynamic range (up to five decades). Ideally, they should also be able to probe the elemental distribution and to provide information on chemical bonding. In this Thematic Series, we present the work of various leading labs in developing such techniques. Targeting 2-D/3-D resolution, one inevitably needs to look at scanning probe techniques that can be proclaimed to be dominant for electrical characterization and atomic probes that can be viewed as the ultimate in terms of compositional analysis. At the same time we need to recognize that, notwithstanding the past efforts and achievements, there remains a considerable knowledge and performance gap between the state-of-the-art metrology and the future metrology requirements. Hence also some simulation work is presented in this Thematic Series. Pierre Eyben Leuven, April 2013

On the extension of ET-FDSOI roadmap for 22 nm node and beyond

With the current scenario of different candidates to lead the road to 14nm node and beyond, this work presents a thorough Multi-Subband Ensemble Monte Carlo (MS-EMC) study of the scaling possibilities of Extremely Thin Silicon on Insulator technology (ETSOI) considering the impact of Buried Oxide (BOX) engineering on the electrostatic integrity of devices addressed for the forthcoming technological nodes. The simulations show that the combined use of Ultra Thin BOX (UTBOX) and Ground Plane/Back Bias (GP/BB) plane are enabling techniques to ensure an adequate control of Short Channel Effects (SCEs) in order to extend the roadmap of ETSOI technology down to 11nm node and beyond. BOX engineering also makes possible a redefinition of standard scaling rules relaxing the constraints on LG/TSi ratio with the advantage over Multiple Gate FETs (MuGFETs) based architectures of a fully compatible fabrication process with main stream planar technologies.

Effects of Gate Oxide and Junction Nonuniformity on the DC and Low-Frequency Noise Performance of Four-Gate Transistors

The effects of imperfections on the electrical performance of four-gate field-effect transistors (G4-FETs) have been studied. Variations in the oxide trap distribution and in the metallurgical boundary of the junction gates impact the low-frequency noise and the static (dc) performance of the G4-FET. By modeling, iterative characterization of published experimental data, and extensive simulations, it is shown that these effects originate from trap distributions in the gate oxides and in the depleted regions of the semiconductor channel. The proposed models are based on established models, such as the unified flicker noise model, with modifications and improvements that extend to trap distributions with gradients, variable frequency slope α of 1/fα noise spectra, and are applicable for gate stacks with high-k dielectrics, such as HfO2 and HfSiON. The characterization procedures allowed for identifying optimum profiles of the metallurgical boundary of junction gates, which simultaneously improve the dc and noise performances of the G4-FET, such as subthreshold swing and low noise. The results indicate the importance of the precise control of depletion and conduction in the channels of multiple-gate FETs.

Multiple Gate Field-Effect Transistors for Future CMOS Technologies

This is a review paper on the topic of multiple gate field effect transistors: MuGFETs, or FinFETs, as they are called. First, the motivation behind multiple gate FETs is presented. This is followed by looking at the evolution of FinFET technologies; the main flavors (variants) of multigate FETs; and their advantages/disadvantages. The physics and technology of these devices is briefly discussed. Results are then presented which show the performance figures of merit of FinFETs, and their strengths and weaknesses. Finally, a perspective on the future of the FinFET technology is presented. This paper is a judicious mix of the author’s original work on FinFETs and other contemporary know-how available in the literature on this topic.

Cross-Section Features Influence on Surrounding MuGFETs

This work presents a study of the cross-section features (such as shape and dimensions) impact on surrounding multiple-gate FETs (MuGFETs) performance. Bearing this objective in mind, the results discussion was based on the analysis of very important parameters, such as the subthreshold slope and the threshold voltage, as a function of the transistors physical characteristics for different cross-section shapes. Considering, at first, surrounding devices with the same silicon thickness, the best results were obtained by the circular channel cross-section, when compared to square and octagonal ones. On the other hand, this work highlighted the impact of the dimensions in this cross-section shape comparison. Focusing on circular and square-shaped devices, it was observed that the latest one may present better short channel effects, depending on the cross-section area. In other words, the geometric optimization in terms of channel current control must take into account different cross-section features, such as the area and the cross-section shapes.

Total-Dose Effects Caused by High-Energy Neutrons and $\gamma $-Rays in Multiple-Gate FETs

This work investigates the effects of high-energy neutrons and γ-rays on multiple-gate FETs with different geometries (notably gate lengths down to 50 nm). The impact of radiation on device behavior is addressed through the variation of parameters such as threshold voltage, subthreshold slope, transconductance maximum and DIBL. It is shown that degradations caused by γ-rays and high-energy neutrons with similar doses are largely similar. It is revealed that, on the contrary to the generally-believed immunity to irradiation, very short-channel FinFETs can become extremely sensitive to the total dose effect. The possible reasons are discussed.

Multiple Gate Field-Effect Transistors for Future CMOS Technologies

AbstractThis is a review paper on the topic of multiple gate field effect transistors: MuGFETs, or FinFETs, as they are called. First, the motivation behind multiple gate FETs is presented. This is followed by looking at the evolution of FinFET technologies; the main flavors (variants) of multigate FETs; and their advantages/disadvantages. The physics and technology of these devices is briefly discussed. Results are then presented which show the performance figures of merit of FinFETs, and their strengths and weaknesses. Finally, a perspective on the future of the FinFET technology is presented. This paper is a judicious mix of the author’s original work on FinFETs and other contemporary know-how available in the literature on this topic.

Effect of high-energy neutrons on MuGFETs

This paper investigates, for the first time, the influence of high-energy neutrons on Multiple-Gate FETs (MuGFETs) with various gate lengths and fin widths. Neutron-induced degradation is addressed through the variation of major device parameters such as threshold voltage, subthreshold slope, maximum transconductance and DIBL. We demonstrate that high-energy neutrons result in total-dose effects largely similar to those caused by γ- and proton-irradiations. It is shown that, contrarily to the generally-believed immunity to irradiation, very short-channel MuGFETs can become extremely sensitive to the total-dose effect. The possible reasons of such length-dependent neutron-induced degradation are discussed and finally related to gate edges.

Performance improvement in narrow MuGFETs by gate work function and source/drain implant engineering

At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short channel effect (SCE) control than their bulk Si counterpart [Doyle BS et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 2003;24(4):263–5, van Dal MJH et al. Highly manufacturable FinFETs with sub-10 nm fin width and high aspect ratio fabricated with immersion lithography. In: VLSI Symp Tech Dig; 2007. p. 110–1 [1,2]]. In addition, their undoped channels allow a substantial reduction of the threshold voltage ( V T) mismatch, which makes the MuGFET an excellent candidate for replacing planar MOSFETs in SRAM structures. However, as the Si fin width ( W fin) and gate length ( L g) are down-scaled in order to improve the SCE control and current drive, respectively, the gate work function and access resistance ( R SD) engineering become more challenging. In this paper, two approaches for optimizing the performance of narrow MuGFETs are reported and analysed: the first one relies on the thickness of their Plasma-Enhanced-ALD (PE-ALD) TiN gate electrode. It is demonstrated that very thin PE-ALD TiN gate electrodes allow improved SCE control and enhanced performance in nMOS MuGFETs. The second approach relies on non-amorphizing ion (boron) implantations for both extension and HDD implantations. A substantial R SD reduction is demonstrated for pMOS MuGFETs with Si fin widths down to 10 nm.

Preparation, Characterization, and Damage-Free Processing of Advanced Multiple-Gate FETs

Preparation, Characterization, and Damage-Free Processing of Advanced Multiple-Gate FETs

Minimization of MuGFET source/drain resistance using wrap-around NiSi-HDD contacts

Inherently smaller cross-sectional area of heavily doped source/drain regions (HDDs) in multiple gate transistors is known to give rise to a higher contact resistance between Si and HDD silicide as compared to a planar transistor with similar width of the Si channel. In order to characterize the contact resistance, multiple gate FETs have been fabricated with fin widths and gate lengths down to 18 and 45nm, respectively. Experiments performed by varying layout and technology parameters show that Nickel silicide forms wrapped contacts around HDDs. Further, the silicidation process is shown to be fully siliciding HDDs in devices with narrow fins, where a selective epitaxial growth of Si has been performed in HDDs.

TRACE—traceability and reliability assuring computerized environment : Koji Ohtoriet al. Proceedings of the 21st Symposium on Reliability and Maintainability, Japan, 25 (June 1991)

At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short channel effect (SCE) control than their bulk Si counterpart [Doyle BS et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 2003;24(4):263–5, van Dal MJH et al. Highly manufacturable FinFETs with sub-10 nm fin width and high aspect ratio fabricated with immersion lithography. In: VLSI Symp Tech Dig; 2007. p. 110–1 [1], [2]]. In addition, their undoped channels allow a substantial reduction of the threshold voltage (VT) mismatch, which makes the MuGFET an excellent candidate for replacing planar MOSFETs in SRAM structures. However, as the Si fin width (Wfin) and gate length (Lg) are down-scaled in order to improve the SCE control and current drive, respectively, the gate work function and access resistance (RSD) engineering become more challenging.In this paper, two approaches for optimizing the performance of narrow MuGFETs are reported and analysed: the first one relies on the thickness of their Plasma-Enhanced-ALD (PE-ALD) TiN gate electrode. It is demonstrated that very thin PE-ALD TiN gate electrodes allow improved SCE control and enhanced performance in nMOS MuGFETs. The second approach relies on non-amorphizing ion (boron) implantations for both extension and HDD implantations. A substantial RSD reduction is demonstrated for pMOS MuGFETs with Si fin widths down to 10 nm.