Multimicroprocessor System Research Articles

Reliability of multi-microprocessor system with complicated switching

Reliability of multi-microprocessor system with complicated switching

Dual architecture of an intelligent multimicroprocessor system with a multidimensional neural-ensemble structure

Dual architecture of an intelligent multimicroprocessor system with a multidimensional neural-ensemble structure

Neural growing networks as a model of an intelligent multimicroprocessor system with a neuron-ensemble structure

This paper considers some issues of construction of intelligent multimicroprocessor systems on the basis of neural growing networks.

Vision processor system for moving-object analysis

This paper proposes a vision processor for moving-object analysis in time-varying images. The process of motion analysis can be divided into three stages: moving-object candidate detection, object tracking, and final motion analysis. The processor Consists of three components corresponding to these three stages. The first isan overall image processing unitwith local parallel architecture. It locates candidate regions for moving objects. The second is a multimicroprocessor system consisting of 16 local modules. Each module tracks one candidate region. The third is the host workstation. In this paper, we describe both the architecture and the software of the vision processor.

A Multimicroprocessor System with Hierarchical Bus Organization

A Multimicroprocessor System with Hierarchical Bus Organization

Design and implementation of a multi-microprocessor architecture for image processing

A multi-microprocessor system prototype has been developed for use in image processing applications. A linear array of processors is interfaced to a two-dimensional SRAM array with a row/column access topology. Off processor control logic is implemented to coordinate parallel conditional branching and looping statements in an otherwise SIMD architecture known as the Access Constrained Memory Array Architecture (ACMAA). Our prototype consists of a two-element processor array interfaced to a 2 × 2 SRAM array and is used to estimate the performance of larger systems. Architecture specific algorithms for 2-D convolution and edge detection are studied in depth. The system's performance is analysed in the context of these algorithms, and a near optimum speed-up is achieved.

車両のアクティブ制御

The purpose of this study is to research the feasibility of an integrated autombile control system, which has various control functions realized by conventional 4WS, ABS, etc. For this purpose we developed a new drive control system in which front wheels are driven by an engine, while rear wheel are driven by two electric motors. Yaw rate control yields additional moment by drive force differrence between two rear wheels. Slip control regulates the slip ratio of each rear wheel. Motor control executes high speed torque control. These controls are performed by a sophisticated multi-microprocessor system. The following results have been derived; (1) The robustness against disturbances caused by external forces was improved. (2) The acceleration and braking capabilities on low friction roads were improved. (3)The cornering stability on low friction roads was augumented by distributing the driving forces appropriately onto three drive axles.In conclusion, this study has revealed that various automobile control functions can be integrated in a single mechanism by means of independent wheel drive system.

Image processing experiments on a multi-microprocessor system

This paper presents the design of a multi-microcomputer which provides the basis of a system useful for processing large numbers of images. We present the architecture, the features of the operating system and experimental results. This system consists of a central computer and a number of satellite microcomputers. Communication between the central computer and each satellite is accomplished through dual-ported RAMs. It is a single bus system with a ‘star’ architecture, which under certain conditions can simulate other architectures. We have developed an operating system that allows our multicomputer system to be used in ‘user’, ‘star’, ‘queue’ and ‘pipeline’ processing modes. These processing modes allow the user to configure a powerful queueing multicomputer system. This paper presents models that predict the throughput of the system, and reports on an extensive set of experiments that are designed to test the system and verify its performance increase as a function of the number of satellites.

A multiprocessor system for dynamic system simulation

The basic goal of the project reported in. this paper was to design and implement an experimental multimicroprocessor system dedicated to the real-time parallel simulation of dynamic systems of various degrees of complexity. The implemented multimicroprocessor called RAMS is also used to study the parallelization concepts of dynamic system models. Potential applica tion of RAMS is in the process control area. The RAMS hardware architecture and software concepts, in particular the auto matic synthesis of RAMS application software, are given in some detail. The problems of both task creation and schedul ing in the non-deterministic RAMS environment are addressed. The experimen tal results show the power of RAMS through the parallel simulation of a case study dynamic system.

Multimicroprocessor system for online monitoring in a CCU

A real-time monitoring system for physiological signals, developed for patients in coronary care units (CCUs), is described. This system monitors the signals that have the greatest clinical value in a CCU environment (ECG and cardiovascular pressures), taking charge of detecting dangerous situations and of extracting information significant to the correct monitoring of the patient. The information it extracts, mainly from the ECG, is presented to the user in an ergonomic way using written reports and graphs which collect and compile the information, facilitating its interpretation. Some utilities have been developed to allow the user to modify certain monitoring conditions as well as to correct results derived from them, thereby improving the reliability of the monitoring process. The system uses a multimicroprocessor architecture (imposed by the need to perform a large number of tasks in real time) with a block based on the VME bus, charged with acquiring and processing the monitored signals, and an IBM-compatible PC/XT which is used as a system user interface and a massive storage device in which the information resulting from the monitoring of signals is stored.

A new DMA method for single- and multimicroprocessor systems

The authors present a new DMA system where the CPU need not be kept inactive during the clock cycles where the direct memory access is performed. The method is especially interesting because it allows simultaneous data processing and transmission and in particular to the signal processing from integrated sensor systems (ISS). The procedure is based on the sharing of the RAM memory by the CPU and the DMA controller, so both of them can read or write in memory during the same clock cycle without conflict. This simple but powerful method is easily compatible with a multimicroprocessor system based on a shared memory structure.

Crossbar switch backplane and its application

A crossbar switch backplane design (bus switch backplane) is described. This backplane holds a maximum of 16 modules and allows simultaneous communications between up to eight pairs of modules. The aggregate data transfer rate on the backplane is 160 Mb/s. The bus switch backplane is an essential part of the Advanced Computer Program (ACP) Multiple Array Processor, a superconductor for site-oriented problems. The first application of this machine is in lattice gauge theory calculations. The bus switch backplane also finds ready application in data acquisition schemes based on the ACP multimicroprocessor system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A multiprocessor architecture and its application to adaptive control

The paper presents the use of a multimicroprocessor system in adaptive control applications. The system is a global memory multiprocessor with a single shared bus. Processes executed on different processing units exchange messages through the global memory. Adaptive control algorithms have been split into two processes which are executed in parallel and co-ordinate each other by means of suitable data exchanging. The effectiveness of this implementation has been outlined in the cases when the reduction of sampling period is the major concern. Experiments on a laboratory process simulator have shown that a better steady state behaviour and/or a faster adaptivity can be obtained.

A multi-microprocessor system for the control of robot welders

This paper deals with a multi-microprocessor system to solve problems due to the increasing complexity of robotic welding process, and associated models. The system functions are analysed and a design is obtained by partitioning the system controller into functional blocks. Six processing units are defined and designed to support the implementation of those functional blocks and to accomodate parallel processing operations. A low refresh time of 5 ms is obtained in controlling the overall system.

Performance Evaluation Method for interprocessor interrupts by message passing

A performance evaluation method for an inter-processor interrupt mechanism in a shared bus multi-microprocessor system is studied. In this mechanism, each processor has a register, i.e. message box, to which other processors can write a message via a shared bus. In addition, each message written into a processor's message box causes an interrupt. A generalized stochastic Petri net (GSPN) model is proposed for analyzing the above mechanism's behavior.

A modular multi-microcomputer system for on-line vibration diagnostics

A new modular multi-microprocessor system for on-line vibration monitoring and diagnostics of PWRs is described. The aim of the system is to make feasible an early detection of increasing failures in relevant regions of a reactor plant, to verify the mechanical integrity of the investigated components, and to improve therefore the operational safety of the plant. After a discussion of the implemented surveillance methods and algorithms, which are based on hierarchical structured identification (estimation) and statistical pattern recognition tools, the system architecture (software and hardware) is portrayed. The classification scheme itself works sequential so that samples (or features) can arrive on-line. This on-line classification is important in order to take necessary actions in time. Furthermore, the system has learning capabilities, which means it is adaptable to different, varying states and plant conditions. The main features of the system are presented and its contribution to an automation of complex surveillance and monitoring tasks is shown.

Event-driven debugging for distributed software

Debugging of distributed software is approached in this paper by defining specific classes of program events to be monitored by the user while execution is in progress. An elementary event is defined in terms of a range condition and an access mode for a memory location. The concept of a compound event is introduced, expressed in terms of either an accumulated event, a sequential event conjunction, a logical event disjunction or an instantaneous event conjunction. On the occurrence of an event, the actions connected with that event will be performed. Possible actions are trace and break traps, event counting and measurement of time intervals. A specific debugger designed for a realtime multimicroprocessor system and based on the event-action model is presented.

A versatile Kernel proposal for a multimicroprocessor system environment

This paper describes an approach toward the design principles of a versatile kernel for a tightly coupled multimicroprocessor operating system. Mechanisms are presented for the processes running in parallel. These kernel mechanisms provide facilities to allow for the creation and internal representation of processes, protected passing of control, and resource sharing among a set of processes utilizing a pool of microprocessors. In designing the proposed kernel the methodology followed is to decompose user programs into groups of processes that are eligible to be executed simultaneously. This decomposition is effected by information obtained both at compile time and at run time.

Multiprocessing memory subsystem

This paper presents a central memory subsystem for a tightly coupled multimicroprocessor system. The design supports high-speed single-cycle and burst-mode data transfers. It supports a high level of data integrity through autonomous retries upon error detection, and provides a high level of test support. The multiprocessor system employs a distributed cache using the VMEbus. The memory subsystem has special facilities to guarantee data consistency in the different caches.

Vampix, a multimicroprocessor control system adaptable to special complex machines

This paper describes the VOEST-ALPHINE Multimicroprocessor Industrial Control system VAMPIX, which has been designed to control any type of machinery which is used in industrial manufacturing. It combines features of customary control systems with highly modern multiprocessor technology. It meets the requirements for control systems such as robust construction and good adaptibility to changes in the machine design by using a highly modular structure.