Abstract
A multi-microprocessor system prototype has been developed for use in image processing applications. A linear array of processors is interfaced to a two-dimensional SRAM array with a row/column access topology. Off processor control logic is implemented to coordinate parallel conditional branching and looping statements in an otherwise SIMD architecture known as the Access Constrained Memory Array Architecture (ACMAA). Our prototype consists of a two-element processor array interfaced to a 2 × 2 SRAM array and is used to estimate the performance of larger systems. Architecture specific algorithms for 2-D convolution and edge detection are studied in depth. The system's performance is analysed in the context of these algorithms, and a near optimum speed-up is achieved.
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