Abstract
A performance evaluation method for an inter-processor interrupt mechanism in a shared bus multi-microprocessor system is studied. In this mechanism, each processor has a register, i.e. message box, to which other processors can write a message via a shared bus. In addition, each message written into a processor's message box causes an interrupt. A generalized stochastic Petri net (GSPN) model is proposed for analyzing the above mechanism's behavior.
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