Multimicroprocessor System Research Articles

A Fully Digitalized Speed Regulator using Multimicroprocessor System for Induction Motor Drives

A fully digitalized speed regulator is proposed which executes all regulatory processing by using a multimicroprocessor. The hardware configuration of the regulator is standardized. A vector control algorithm is used to perform fast response speed control of an induction motor. Microprocessors execute a PWM gate pulse generation and current component detection in addition to speed control processing. In applications of the regulator to a 1.5-kW induction motor drive system, Its effectiveness is confirmed.

Microprocessor Control of a Cycloconverter

This paper examines in some detail the problem of controlling a single-phase cycloconverter using a multimicroprocessor system. The cycloconverter must operate with a frequency- and voltage-wild input waveform. A new control scheme based upon input areas has been devised to enable successful operation under such circumstances. Both the hardware and software aspects of the microprocessor controller are described, including details of the area algorithms.

Parallel processing of robot-arm control computation on a multimicroprocessor system

A parallel-processing scheme is described for robot-arm control computation on any number of parallel processors. The scheme employs two multiprocessor scheduling algorithms called, respectively, depth first/implicit heuristic search (DF/IHS) and critical path/most immediate successors first (CP/MISF); these were recently developed by the authors. The scheme is applied to the parallel processing of dynamic control computation for the Stanford manipulator. In particular, the proposed algorithms are applied to the computation of the Newton-Euler equations of motion for the Stanford manipulator and implemented on a multimicroprocessor system. The test result was so successful that the use of six processor pairs in parallel could attain the processing time of 5.37 ms. It is also shown that the proposed parallel-processing scheme is applicable to an arbitrary number of processors.

並列制御機構によるマニピュレータの制御

A multi-microprocessor system (N-1) has been developed for machinery control. It is composed of 64 microprocessor units and an inter-processor communication system. Main objectives of N-1 are (1) to realize clear software structure by using dedicated processors for independent functions, (2) to make it possible to execute complicated tasks in real time by means of parallel processing capability and (3) to realize high reliability through redundant configuration. N-1 is connected with a manipulator which has six joints in order to investigate its performance. Parallel software for manipulator control and fault tolerant processing are developed and implemented on N-1. It is confirmed by experiments and analysis that N-1 has enough processing capability and flexibility to realize the main objectives.

Real-time waveform analysis of multichannel nerve impulses with a multimicroprocessor system.

A new system for the online real-time waveform separation of the nerve impulses recorded from multichannel extracellular electrodes placed to the peripheral nerve trunk has been developed using two microprocessors and a graphics computer. One microprocessor (Intel 8085) performs nerve impulse detection and the other (Intel 8086) separates nerve impulses by clustering in the two-dimensional histograms representing the distribution of the parameters extracted from their waveforms. System performance was examined with two channel impulses recorded from the nerve trunk innervating the Sartorius muscle of a frog. These data could be classified into 6–8 different groups in real time.

Organization of computational process in solving applied problems on a recursive multimicroprocessor system

Organization of computational process in solving applied problems on a recursive multimicroprocessor system

Use of the Fermilab Advanced Computer Program Multi-Microprocessor as an on-Line Trigger Processor

The Fermilab Advanced Computer Program is constructing a powerful multi-microprocessor system for data analysis in high-energy physics. The system will use commercial 32-bit microprocessors and be programmed in Fortran-77. A large array of support software allows easy migration of user applications from a uniprocessor environment to the multiprocessor, as well as providing sophisticated program development, debugging, and error handling and recavery tools. This system will provide computing power with a cost effectiveness of $3000-4000 per VAX 11/780 equivalent. We describe here the applications of this system as an on-line trigger processor. The low cost, commercial availability, compatibility with off-line analysis programs, and high data bandwidths (up to 160 MByte/sec) make this system an ideal choice for such real-time applications.

A family of compatible single- and multimicroprocessor systems with 8-bit and 16-bit microprocessors

In the paper, a multimicroprocessor system for 8-bit and 16-bit microprocessors is presented. The main assumptions of the project of the presented system are discussed. Different single- and multimicroprocessor structures with 8-bit and 16-bit microprocessors are outlined. A detailed description of two single-board microcomputers and system aspects of different solutions are presented. Finally, an intelligent floppy disk controller is described.

PASM

PASM is a multifunction partitionable SIMD/MIMD system being designed at Purdue for parallel image understanding. It is to be a large-scale, dynamically reconfigurable multimicroprocessor system, which will incorporate over 1,000 complex processing elements. Parallel algorithm studies and simulations have been used to analyze application tasks in order to guide design decisions. A prototype of PASM is under construction (funded by an equipment grant from IBM), including 30 Motorola MC68010 processors, a multistage interconnection network, five disk drives, and connections to the Purdue Engineering Computer Network (for access to peripherals, terminals, software development tools, etc.). PASM is to serve as a vehicle for studying the use of parallelism for performing the numeric and symbolic processing needed for tasks such as computer vision. The PASM design concepts and prototype are overviewed and brief examples of parallel algorithms are given.

An Advanced Communication Protocol for the Proposed IEEE 896 Futurebus

With its asynchronous protocol, the proposed IEEE 896 Futurebus achieves an extended design life, unequaled performance, and unprecedented flexibility. Its design eliminates many of the problems traditionally associated with multimicroprocessor system buses.

Integrated Simulation System for Design and Evaluation of Distributed Computer Control Systems

This paper presents an integrated simulation system to be used for the design and evaluation of distributed computer control systems. The simulation system is comprised of Communication Performance Evaluation Module, System Reliability Evaluation Module and Control Performance Evaluation Module. Different from conventional all-software approaches, dedicated hardware facilities such as a parallel multimicroprocessor system for real-time simulation of controlled system dynamics and a mimic communication system are used advantageously to achieve best overall economy of simulation in conjunction with software simulation modules. The features of the proposed of simulation system as applied to several distributed computer control systems with different system architectures are described.

A Multimicroprocessor System for Fault Tolerant Control of an Articulated Mechanism

A multiprocessor system consisting of three processors built for reliable control of an electrically powered leg (the OSU Monopod) is described. All computations are done in a redundant fashion by two processors. Results are then compared by a different pair of processors, and all three processors participate in the identification of the faulty processor in case of a disagreement of the two sets of results. The system is reconfigured when one of the computers fails. Comparison and fault diagnosis are done by software.

The control of an astronomical telescope using a multimicroprocessor system

This paper describes a novel application of a multimicroprocessor system which is specifically suited to many low-cost real-time applications. The system described was developed to control an astronomical telescope. It is based on a twin microprocessor configuration, the two microprocessors being organized in master/slave roles. The master microprocessor deals with input/output and numerical functions while the slave drives the stepping motors. Communication between the two is achieved through interleaving access to common memory. The design requirements of the astronomical telescope are introduced with emphasis on the specific requirements of the astronomers. A brief summary of alternative pulse generation systems is presented. Hardware and software design details of the telescope system are then discussed. The paper concludes with several suggestions for further applications of multimicroprocessor systems.

Analysis of a multi-microprocessor system with time-shared bus

The method of the multimicroprocessor system analysis is described in this paper. The analysed multimicroprocessor system can be treated as a singular microprocessor with the increased computing power. As a mathematical model the discrete Markov chain is used. This model allows to obtain the required system's parameters such as conflict probability and efficiency. The computing results for multimicroprocessor systems are also presented.

A pipelined multimicroprocessor system for on-line compiling

Programming languages tend to be more and more frequently interpreted rather than compiled. This is mainly because hardware is becoming cheaper and newer hardware with a still higher degree of complexity is rapidly appearing. The well-known separation of interpretation and execution is used together with an intermediate code to present a technique which achieves an important improvement in program execution speed. The solution given involves a highly interactive multiprocessor with extremely short parallel processes. A pipelining system at the level of the intermediate code together with a first-in first-out queuing buffer is used. Our proposal amounts to combining a set of microprocessors into a multiprocessor system. The set consists of an interpretation processor and one or more execution processors. The execution processors run a code that is free of jumps. The performance thus reaches the level of compiled code. No restriction on intermediate codes is made. However, a complex an powerful code that is not storage consuming will generally speed up the type of machine presented. The machine architecture together with the technological possibilities and the realization of the machine are emphasized in this paper.

A Highly Available Multimicroprocessor System for Real-Time Applications

This paper describes the implementation of a highly available multimicroprocessor system based on the M.A.R.A. (Modular Architecture for Real Time Processing) multimicroprocessor architecture developed by Selenia. The proposed solution is based on the full duplication of a M.A.R.A. node. Fault detection is independently performed on the two nodes. At every time, only one of the two nodes (Master Node) controls the application, while the other node (Slave Node) is always ready to substitute the Master node. In case of a detected fault, the Master node communicates its unavailability to the Slave Node, and disconnects itself from the application. The Slave Node resumes the control of the application starting from the most recent consistent system state. To avoid any loss of application, the Slave Node during normal operation continuously maintains and updates a copy of the system state on the basis of informations provided to it by the Master Node. The application software is structured in atomic transactions. An atomic transaction is intended as a set of actions which updates the system state so that either all the actions have been executed (transaction commit), or none will have been (transaction abort). Therefore in case of a fault in the Master Node, the consistent system state is resumed by the Slave Node by aborting the not yet committed transactions and restoring them; it also completes the commit phases of the transactions which were committing in the Master Node when the fault has happened. The application software is supported by a run-time environment which makes transparent the duplicated configuration of the system.

An Exchange Protocol for Continuous Speech Recognition and Synthesis System

ARIAL II is a project currently under development at Toulouse University to study the connected speech understanding problem. The Speech Recognition and Synthesis System (SRSS) developed in the context of ARIALII has been based on a desire to exploit multiprocessor with multi-task architecture for efficient implementation, and a desire to handle more complex speech task domains with an optimal processing time (Perennou, 1980), (Osman, 1979,1981), The SRSS is organized on three modular sub-systems : 1) Recognition System (RS); 2) Acquisition and Synthesis System (ASS) ; 3) Exchanges and Control Module (ECM). We describe in this paper the ECM functionning and the exchanges protocol between modules and between sub-systems. The functional structure of the SRSS is based on the parallelism of procedures between the different modules on a multi-task hierarchical architecture (Anceau, 1974), (C.G. Bell and all, 1971,1973), (D.R. Reddy and all, 1970). The RS mainfram computer is coupled with the ASS by means of the ECM communication network.control and processing tasks are distributed between the mainfram computer and the multi-microprocessor (ASS-ECM) system according its nature and complexity. The data transfer between ASS and RS is performed with a 1 M bytes/s speed, by means of a direct memory access controler (DMAC).

Multilayer Algorithms for On-line Control of Nonlinear Disturbed Dynamic Processes and their Implementation on a Multi-microprocessor System

For the optimal control of a linear system with measurable or observable disturbances according to a quadratic criterion it is possible (with assumptions which are reasonable for practical applicability) to decompose the central feedforward-feedback solution into a two-layer control consisting of a superordinate on-line static feedforward optimization (depending on the disturbances) and a subordinate optimal dynamic transition into the actual static-optimum state (by means of state feedback). These results hitherto obtained are extended in this paper to nonlinear dynamic processes of the Hammerstein-type. With regard to the implementation on a multi-microcomputer-system, time-discrete algorithms are exclusively taken into consideration. After setting up the optimal central feedforward-feedback control for a linear system, a multilayer algorithm is developed for the on-line control of a nonlinear Hammerstein-process by heuristically applying the decomposition derived for linear systems (explained above). After that, an optimal time-discrete state observer for a Hammerstein-process is constructed. Finally some explanations are given concerning the implementation of the multilayer algorithm on a multicomputer system comprising problems of the hardware structure and those of the software design.

Feasibility of a Distributed Computer Traffic Control System

The feasibility of implementing a realtime, distributed computer, traffic control system is investigated in this paper. A centralized multimicroprocessor system is proposed, and an off-line optimization algorithm SIGOP II is chosen from existing algorithms and is modified for use in a distributed system.The modified program was run on a Motorola MC6800 microprocessor and the characteristics of the output are discussed. The memory requirement and execution time of the program are found to be acceptable and will not be an obstacle towards building such a distributed system.

Operating Systems for the Micronet Network Computer

The Micros operating system executes on a modular multimicroprocessor system. It provides system-wide high-level control as well as local operating systems for individual nodes.