Abstract

ARIAL II is a project currently under development at Toulouse University to study the connected speech understanding problem. The Speech Recognition and Synthesis System (SRSS) developed in the context of ARIALII has been based on a desire to exploit multiprocessor with multi-task architecture for efficient implementation, and a desire to handle more complex speech task domains with an optimal processing time (Perennou, 1980), (Osman, 1979,1981), The SRSS is organized on three modular sub-systems : 1) Recognition System (RS); 2) Acquisition and Synthesis System (ASS) ; 3) Exchanges and Control Module (ECM). We describe in this paper the ECM functionning and the exchanges protocol between modules and between sub-systems. The functional structure of the SRSS is based on the parallelism of procedures between the different modules on a multi-task hierarchical architecture (Anceau, 1974), (C.G. Bell and all, 1971,1973), (D.R. Reddy and all, 1970). The RS mainfram computer is coupled with the ASS by means of the ECM communication network.control and processing tasks are distributed between the mainfram computer and the multi-microprocessor (ASS-ECM) system according its nature and complexity. The data transfer between ASS and RS is performed with a 1 M bytes/s speed, by means of a direct memory access controler (DMAC).

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