Multiple-valued Logic Research Articles

Special issue on logics and artificial intelligence

Abstract There is a significant range of ongoing challenges in artificial intelligence (AI) dealing with reasoning, planning, learning, perception and cognition, among others. In this scenario, many-valued logics emerge as one of the topics in many of the solutions to some of those AI problems. This special issue presents a brief introduction to the relation between logics and AI and collects recent research works on logic-based approaches in AI.

Development of Programmable Logic Array for Multiple-Valued Logic Functions

The binary information technology reaches its limits set by the atomic size miniaturization, by calculation speed and by the fundamental principle of energy dissipation per bit processing. Employing multiple-valued logic (MVL) cells as computing and memory units reduces energy losses and enables to pack of unprecedented high-density information, but the current silicon-based material technologies have been studied marginally for the material realization of MVL devices. Here, we propose to use the ferroelectrics for the implementation of MVL units using their ability to pin the polarization as a sequence of multistable states. More specifically, the realization of a programmable logic array (PLA) based on MVL units is considered with the application of the ferroelectrics technology in implementation of memory units. The specific of the PLA construction is the use of generalized Reed-Muller expression for the representation of an MVL function. In this article, several possible implementations of such PLAs are considered, and their properties are analyzed from the logic design point of view.

Valid Arguments and Heyting Algebra using Multi Valued Logic

Over last three decades, multi valued logic (MVL) has been receiving considerable attention. So, we focus our concentration upon multi valued logic using some of the rules of mathematical logic, which can be used in developing artificial intelligence. Since Aristotle’s logic there were only two propositions. Later it was extended to n-valued logical proposition which is greater than 2, that is popularly known as multi valued logic proposition – they are true, false and unknowns. In this paper we will discuss about multi valued logic with 27- possible using Jaina logic and some of the rules as it gives the best results. In Jaina Logic, indeterminant means something which cannot describe more than one aspect at a time. So, we are going to consider each aspect separately and assign True or False. Then according to the given condition we can either apply min or max condition to get a precise solution.

Functionalized Organic Material Platform for Realization of Ternary Logic Circuit.

Negative differential resistance/transconductance (NDR/NDT) has been attracting significant attention as a key functionality in the development of multivalued logic (MVL) systems that can overcome the limits of conventional binary logic devices. A high peak-to-valley current ratio (PVCR) and more than double-peak transfer characteristics are required to achieve a stable MVL operation. In this study, an organic NDR (ONDR) device with double-peak transfer characteristics and a high peak-to-valley current ratio (PVCR; >102) is fabricated by utilizing an organic material platform for the development of a key element device for MVL applications. The organic NDT (ONDT) device is fabricated using a series connection of electron-dominant (P(NDI2OD-Se2)) and hole-dominant (P(DPP2DT-T2)) channel ambipolar organic field-effect transistors (AOFETs), and the NDR feature is achieved via correlated biasing of the ONDT device. The PVCR of the ONDT device can reach up to 13,000 via carrier transfer modulation of the AOFETs by varying the PMMA:P(VDF-TrFE) ratio of the mixed layer that is used as the top-gate dielectric of each AOFET. Further, ternary latch circuit operation is demonstrated using the developed ONDR device that stores three logic states with three distinct and controllable output states by adjusting the PMMA:P(VDF-TrFE) ratio of the dielectric layer.

CNFET-based designs of Ternary Half-Adder using a novel “decoder-less” ternary multiplexer based on unary operators

Multi-valued logic (MVL) has more than two-valued logic to decrease the interconnections and energy consumption. Also, the market has seen a significant increase in portable electronics and embedded systems, which depend on batteries. Therefore, this paper proposes 32 nm channel CNFET-Based a Ternary Half Adder (THA) and a “decoder-less” Ternary Multiplexer (TMUX) using the proposed Unary Operator aiming to decrease the power-delay product (PDP) to preserve battery consumption; Simulations performed using the HSPICE simulator for voltage variation, temperature variation, and frequency variation. The results demonstrate the advantage of proposed models with a reduction of 46.4% in transistors count for the THA and 57.3%, and 99.3% in energy consumption (PDP) for the TMUX, and THA, respectively. Moreover, the noise immunity curve (NIC) and Monte Carlo analysis for major process variations (TOX, CNT Diameter, CNT's Count, and Channel length) were studied. The results confirmed that the proposed THA had higher robustness and higher noise tolerance, among other designs.

Design of Ternary Logic and Arithmetic Circuits Using GNRFET

Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional and other emerging device technologies, Graphene Nano Ribbon Field Effect Transistor (GNRFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties of the GNRFET, e.g., the ability to control the threshold voltage by changing the width of the GNR. Variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit. This paper introduces a design approach for ternary logic gates and circuits using MOS-type GNRFET. The designs of basic ternary logic gates like inverters, NAND, NOR, and ternary arithmetic circuits like the ternary decoder, 3:1 multiplexer, and ternary half-adder are demonstrated using GNRFET. A comparative analysis of the GNRFET based ternary logic gates and circuits and those based on the conventional CMOS and CNTFET technologies is performed using delay, total power, and power-delay-product (PDP) as the metrics. The simulation and analysis are performed using the H-SPICE tool with a GNRFET model available on the Nanohub website.

A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to consider multiple-valued logic (MVL) alternatives. Features of Carbon Nanotube Field-Effect Transistors (CNTFETs) make this technology a potential candidate to implement MVL circuits. In this article, a new systematic methodology is proposed to design ternary logic block circuits based on CNTFETs. The methodology is applied to the design of two basic logic circuits, a half adder and a 1-digit multiplier, which are evaluated through HSPICE simulations. Simulation results indicate improvements over current equivalents in transistor count and PDP mean with the half adder version of 19.2%, and 74.07% respectively, and with the 1-digit multiplier of 24.67% and 81.12% respectively.

Comparative performance analysis of FPGA-based MAC unit using non-conventional number system in TVL domain for signal processing algorithm

Today, the complication of binary digital hardware system is progressively growing. Due to this fact, new methodologies for efficiently describing and realising the digital systems are explored in this paper. Multi-valued logic methodology offers a few preferences over existing binary digital system. One of the well-known multi-valued logic systems is ternary value logic (TVL) system. It is seen that all kind of digital signal processing (DSP) algorithms widely use multiply-accumulate (MAC) operation for superior digital processing system. To implement high performance DSP algorithms MAC unit is used extensively. In current scenario, it is seen that non-conventional, non-binary number system-based architecture is also exhibited better performance. The example of such non-conventional, non-binary number systems is ternary residue number systems (TRNSs) and double base ternary number system (DBTNS). Here, a comparative study is made on performance analysis of MAC unit using various non-conventional, non-binary number system. All the architecture is mapped on FPGA for analysis its performance.

Negative differential transconductance device with a stepped gate dielectric for multi-valued logic circuits

Multi-valued logic (MVL) technology is a promising approach for improving the data-handling capabilities and decreasing the power consumption of integrated circuits. This is especially attractive as conventional complementary metal-oxide-semiconductor technology is approaching its scaling and power density limits. Here, an ambipolar WSe2 field-effect transistor with two or more negative-differential-transconductance (NDT) regions in its transfer characteristic (NDTFET) is proposed for MVL applications of various radices. The operation and charge carrier transport mechanism of the NDTFET are studied first by Kelvin probe force microscopy, electrical, and capacitance-voltage measurements. Next, strategies for increasing the number of NDT regions and engineering the NDTFET transfer characteristic are discussed. Finally, the extensibility and tunability of our concept are demonstrated by adapting NDTFETs as core devices for ternary, quaternary, and quinary MVL inverters through simulations, where only WSe2 is employed as a channel material for all devices comprising the inverters. The MVL inverter operation principle and the mechanism of the multiple logic state formation are analyzed in detail. The proposed concept is practically verified by the fabrication of a ternary inverter.

Comparative performance analysis of FPGA-based MAC unit using non-conventional number system in TVL domain for signal processing algorithm

Today, the complication of binary digital hardware system is progressively growing. Due to this fact, new methodologies for efficiently describing and realising the digital systems are explored in this paper. Multi-valued logic methodology offers a few preferences over existing binary digital system. One of the well-known multi-valued logic systems is ternary value logic (TVL) system. It is seen that all kind of digital signal processing (DSP) algorithms widely use multiply-accumulate (MAC) operation for superior digital processing system. To implement high performance DSP algorithms MAC unit is used extensively. In current scenario, it is seen that non-conventional, non-binary number system-based architecture is also exhibited better performance. The example of such non-conventional, non-binary number systems is ternary residue number systems (TRNSs) and double base ternary number system (DBTNS). Here, a comparative study is made on performance analysis of MAC unit using various non-conventional, non-binary number system. All the architecture is mapped on FPGA for analysis its performance.

Comments on “High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits”

In the above article [1] , R. A. Jaber et al. present the designs of ternary logic circuits based on CNTFET technology. The motivation for designing ternary gates is based on the following assumption quoted in the abstract: “Moreover, multi-valued logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption.”

Экстра-понятия и области истинностных значений при интерпретации логических языков в системах искусственного интеллекта

So-called extra concepts introduced to represent structurally defined objects and structures with unlimited complexity in their traditional understanding are suggested. The concepts of extra-word, extra-regular expression, context-free extra-grammar, and context-free extra-language are extensions of the well-known concepts used in the theory of formal languages. Extra words are a special case of symbol sequences; however, the set of all extra words in any alphabet is countable, whereas the set of all symbol sequences is not countable. The periodic codes of rational number representations in some positional numeration system are in fact extra words in this terminology. The concept of an extra-tuple is a generalization of the tuple concept, which implies the possibility of interpreting extra-tuples both as finite and as the indicated type of infinite sequences of elements of an arbitrary, not more than countable set, and it should be noted that the set of all possible sequences of such sort remains countable. By using the introduced concepts, a countable family of the domains of truth values has been specified for multivalued and countable-valued logics, each of which is a bounded lattice of finite or countable power with the traditional definition of basic logical operations of negation, conjunction, and disjunction. The hierarchical construction of the proposed truth domains makes it possible to introduce new logical operations in consideration that do not have analogues in the classical logic.

On the Relationship between Boolean Algebra and Quantum Informatics

The fundamental relationship between quantum physics and discrete mathematics is examined. A method for representing Boolean functions in the form of unitary transformations is described. The question of the connection of Zhegalkin polynomials defining the algebraic normal form of a Boolean function with quantum circuits is considered. It is shown that the quantum information language provides a simple algorithm for constructing the Zhegalkin polynomial based on the truth table. The developed methods and algorithms are generalized to the case of an arbitrary Boolean function with a multibit domain of definition and a multibit set of values, as well as to the case of multivalued ($$k$$-value) logic when $$k = p$$ is a prime number. The developed approach is important for the implementation of quantum computer technologies and is the foundation for the transition from classical computer logic to quantum hardware.

Exploding Individuals: Engaging Indigenous Logic and Decolonizing Science

AbstractDespite emerging attention to Indigenous philosophies both within and outside of feminism, Indigenous logics remain relatively underexplored and underappreciated. By amplifying the voices of recent Indigenous philosophies and literatures, I seek to demonstrate that Indigenous logic is a crucial aspect of Indigenous resurgence as well as political and ethical resistance. Indigenous philosophies provide alternatives to the colonial, masculinist tendencies of classical logic in the form of paraconsistent—many-valued—logics. Specifically, when Indigenous logics embrace the possibility of true contradictions, they highlight aspects of the world rejected and ignored by classical logic and inspire a relational, decolonial imaginary. To demonstrate this, I look to biology, from which Indigenous logics are often explicitly excluded, and consider one problem that would benefit from an Indigenous, paraconsistent analysis: that of the biological individual. This article is an effort to expand the arenas in which allied feminists can responsibly take up and deploy these decolonial logics.

Efficient design of quaternary quantum comparator with only a single ancillary input

Circuit design with no energy dissipation is possible in the reversible logic. Also, using the quantum multiple-valued logic in the design of circuits due to the reduction of circuit width leads to the smaller chip area and lower power consumption. Quaternary reversible logic potentially has several advantages in comparison to the equivalent ternary and binary quantum technologies. Hence, the quaternary quantum technology is a promising choice for the future digital system design. Here, the authors proposed an efficient design of 1-qudit and n -qudit quantum comparators. The comparator module is widely used in search conditions, such as Grover's quantum search algorithm in quantum computing. The proposed circuits were better than their existing counterparts in terms of quantum cost, the number of constant inputs, the number of garbage outputs, and hardware complexity. To design these circuits, they have used 1-qudit gates and 2-qudit Muthukrishnan-Stroud gates. The efficiency of their proposed circuits was reported.

ОЦЕНКИ НЕМОНОТОННОЙ СЛОЖНОСТИ ФУНКЦИЙ МНОГОЗНАЧНОЙ ЛОГИКИ

ОЦЕНКИ НЕМОНОТОННОЙ СЛОЖНОСТИ ФУНКЦИЙ МНОГОЗНАЧНОЙ ЛОГИКИ

Algorithm for constructing logical operations to identify patterns in data

Neural networks have proven themselves in solving problems when the input and output data are known, but the cause and effect relationship between them is not obvious. A well-trained neural network will find the right answer to a given request, but will not give any idea about the rules that form this data. The paper proposes an algorithm for constructing logical operations, in terms of multi-valued logic, to identify hidden patterns in poorly formalized areas of knowledge. As the basic elements are considered many functions of the multi-valued logic of generalized addition and multiplication. The combination of these functions makes it possible to detect relationships in the data under study, as well as the ability to correct the results of neural networks. The proposed approach was considered for classification problems, in the case of multidimensional discrete features, where each feature can take k-different values and is equivalent in importance to class identification.

Design of A High Performance 4-Bit Ternary Multiplier using CNTFET

In digital world, digital circuits are influenced by binary logic. Ternary logic which follows the multiple valued logic concept for designing the logic circuits which is an great alternate to the normal binary logic due to its less power consumption and chip area is reduces. Carbon Nano-tube Field-Effect Transistors (CNTFET) is selected to implement the ternary logic circuits due to its mechanical , electrical and thermal properties. The unique feature of CNTFETs has the potential of getting required threshold voltage by varying the diameter of carbon nano-tubes that makes them as a best appropriate type for implementing the ternary logic. In this paper a 4-Bit Ternary Multiplier is designed using 1-Bit ternary multiplier by CNTFET 32nm technology node and simulated in Hspice tool. The proposed 1-Bit multiplier has 10% less delay and 18% less power than the 1-Bit multiplier proposed by Srivasu et al.

Application of Generalized Reed–Muller Expression for Development of Non-Binary Circuits

Semiconductor devices and binary information technology reach their limits set by the atomic size of miniaturization, calculation speed, and the fundamental principle of energy dissipation per bit processing. Therefore, new technologies in logic design and mathematical approaches must be investigated. Application of multiple-valued logic (MVL) in logic design allows developing gates and circuits with more than two stable states. This enables packing an unprecedented high-density of information. Based on this idea, a new technique of the programmable logic arrays (PLA) construction based on MVL units is considered. The unique aspect of this technique is the application of recurrent generalized Reed–Muller expression (GRME) for MVL function representation. The recurrent procedure for this expression’s construction is considered and applied in the PLA development. The proposed structure of PLA consists of two blocks that are memory and logic block. In this paper, we also consider the possibility to use the ferroelectrics for the implementation of cells of the memory block of PLA. The development of gates with multi-stable states is possible by the ferroelectrics ability to pin the polarization as a sequence of stable states.

A Semantic Multi-Valued Logic for Deforestation Phenomena Interpretation

A Semantic Multi-Valued Logic for Deforestation Phenomena Interpretation