CNFET-based designs of Ternary Half-Adder using a novel “decoder-less” ternary multiplexer based on unary operators

Abstract

Multi-valued logic (MVL) has more than two-valued logic to decrease the interconnections and energy consumption. Also, the market has seen a significant increase in portable electronics and embedded systems, which depend on batteries. Therefore, this paper proposes 32 nm channel CNFET-Based a Ternary Half Adder (THA) and a “decoder-less” Ternary Multiplexer (TMUX) using the proposed Unary Operator aiming to decrease the power-delay product (PDP) to preserve battery consumption; Simulations performed using the HSPICE simulator for voltage variation, temperature variation, and frequency variation. The results demonstrate the advantage of proposed models with a reduction of 46.4% in transistors count for the THA and 57.3%, and 99.3% in energy consumption (PDP) for the TMUX, and THA, respectively. Moreover, the noise immunity curve (NIC) and Monte Carlo analysis for major process variations (TOX, CNT Diameter, CNT's Count, and Channel length) were studied. The results confirmed that the proposed THA had higher robustness and higher noise tolerance, among other designs.