MOSFET Devices Research Articles

Evaluation of Single-Event Effect Current-Carrier Mapping Based on Experimental Data

For single-event radiation damage of power MOSFET devices, this paper aims to establish a statistical analysis method based on external observation (gate/drain current characteristics in irradiation environment) to recognize and evaluate the radiation evolution process and damage mechanism of microscopic physical quantities inside the devices, namely current-carrier (CC) mapping. Firstly, a special data fluctuate–collapse transform analysis method is proposed according to the temporal characteristics of the gate/drain current. Secondly, a carrier dynamic balance ratio based on current data is defined to evaluate the radiation damage degree of the device. TCAD is used to deeply study the relationship between the external current characteristics and the evolution process of internal physical quantities and the damage mechanism. The results show that the current data timing analysis based on fluctuate–collapse transformation can better peer into the evolution process of irradiation events inside the device, and the statistical analysis based on the dynamic balance ratio of carriers can evaluate the severity of irradiation damage to a certain extent.

Ultrathin nanocapacitor assembled via atomic layer deposition

We fabricated ultrathin metal - oxide - semiconductor (MOS) nanocapacitors using atomic layer deposition. The capacitors consist of a bilayer of Al2O3 and Y2O3 with a total thickness of ~10 nm, deposited on silicon substrate. The presence of the two materials, each slab being ~5 nm thick and uniform over a large area, was confirmed with Transmission Electron Microscopy and X-ray photoelectron spectroscopy (XPS). The capacitance in accumulation varied from 1.6 nF (at 1MHz) to ~2.8 nF (at 10 kHz), which is one to two orders of magnitude higher than other nanocapacitors. This high capacitance is attributed to the synergy between the dielectric properties of ultrathin Al2O3 and Y2O3 layers. The electrical properties of the nanocapacitor are stable within a wide range of temperatures, from 25 °C to 150 °C, as indicated by capacitance-voltage (C - V). Since the thickness-to-area ratio is negligible, the nanocapacitor could be simulated as a single parallel plate capacitor in COMSOL Multiphysics, with good agreement between experimental and simulation data. As a proof-of-concept we simulated a MOSFET device with the nanocapacitor gate dielectric, whose drain current is sufficiently high for micro and nanoelectronics integrated circuits, including for applications in sensing.

A Novel Modular Multilevel Converter Topology with High- and Low-Frequency Modules and Its Modulation Strategy

To resolve the issue of the difficultly in effectively balancing the output performance improvement, cost reduction, and efficiency improvement of a medium-voltage modular multilevel converter (MMC), a novel MMC (NMMC) topology based on high- and low-frequency hybrid modulation is proposed in this study. Each arm of the NMMC contains a high-frequency sub-module composed of a heterogeneous cross-connect module (HCCM) and N − 1 low-frequency sub-modules composed of half-bridge converters. The high-frequency bridge arm of the HCCM in this study adopts SiC MOSFET devices, while the commutation bridge arm and low-frequency sub-module of the HCCM adopt Si IGBT devices. For the NMMC topology, this study adopts a high/low-frequency hybrid modulation strategy, which gives full play to the advantages of low switching loss in SiC MOSFET devices and low on-state loss in Si IGBT devices. In addition, a specific capacitor voltage balance strategy is proposed for the HCCM, and the working state of the HCCM is analyzed in detail. Furthermore, the feasibility and effectiveness of the proposed topology, modulation strategy, and voltage balancing strategy are verified by experiments. Finally, the proposed topology is compared with the existing MMC topology in terms of device cost and operating loss, which proves that the proposed topology can better balance the cost and efficiency indicators of the device.

Power Semiconductor Junction Temperature and Lifetime Estimations: A Review

The lifetime of power electronic systems is the focus of both the academic and industrial worlds. Today, compact systems present high switching frequency and power dissipation density, causing high junction temperatures and strong thermal fluctuations that affect their performance and lifetime. This paper is a review of the existing techniques for the electro-thermal modelling of Mosfet and IGBT devices regarding lifetime estimation. The advantages and disadvantages of the methodologies used to achieve lifetime prediction are discussed, and their benefits are highlighted. All the factors required to predict power electronic device lifetime, including Mosfet and IGBT electrical models, the computation of power losses, thermal models, temperature measurement and management, lifetime models, mission profiles, cycle counting, and damage accumulation, are described and compared.

Combined effect of total ionizing dose and electromagnetic pulse on MOSFET devices

Theoretical and experimental research on the combined effect of total ionizing dose (TID) and electromagnetic pulses (EMP) is helpful to develop hardening techniques for semiconductor devices. In this work, a numeric model for the comprehension of the combined effect of TID and EMP on MOSFET devices is developed with the semiconductor device simulation software TCAD. Simulation results show that the NMOS and PMOS devices will exhibit more severe leakage current increase and sub-threshold characteristics degradation in the combined environment. In addition, the potential influence of doping concentration and gate length on the performance of the MOSFET in the combined environment is discussed.

Single Event Effects in 3.3 kV 4H-SiC MOSFETs due to MeV Ion Impact

In this work, MeV alpha particles generated from an accelerator are used to study single event breakdown (SEB) in 4H-SiC MOSFET samples, rated at 3.3 kV. The samples are exposed to bursts of alpha particles under reverse bias conditions to investigate the SEB sensitivity to ion energy and reverse bias. The energies of alpha particles are chosen to reach different depths in the drift region of the MOSFET devices, and also to penetrate the whole drift region. Forward and reverse characteristics are measured after each exposure, as long as no failures occur, to ensure that the device performance is maintained. The measurements show that no significant effects are observed on the drain-source leakage current, while minor effects on gate behavior can be seen as a function of accumulated fluence. Furthermore, SEB can only be triggered with a reverse bias larger than, or equal to 3 kV. A standard MOSFET cell with a similar rated voltage is also simulated in Sentaurus TCAD to study these effects, using two different models for the incident ion-induced ionization: the Alpha Particle and the Heavy Ion model. Simulations show that the Alpha Particle model cannot induce any device failures even with a 3.5 kV reverse bias, while it is possible to trigger a failure by the Heavy Ion model, where the ionization can be selected. Carrier plasma and internal electric field distributions of the two models are plotted and compared, showing that device failures triggered by a heavy ion are related to the hole injection at epi-substrate interface, in which linear energy transfer (LET) of the particle plays an important role.

Investigation of Dead Time Losses in Inverter Switching Leg Operation: GaN FET vs. MOSFET Comparison

This paper investigates the commutation transients of MOSFET and GaN FET devices in motor drive applications during hard-switching and soft-switching commutations at dead time operation. This study compares the switching behaviors of MOSFETs and GaN FETs, focusing on their performance during dead time in inverter legs for voltage source inverters. Experimental tests at various phase current levels reveal distinct switching characteristics and energy dissipation patterns. A validated simulation model estimates the experimental energy exchanged and dissipated during switching transients. The results demonstrate that GaN FETs exhibit lower overall losses at shorter dead times compared to MOSFETs, despite higher reverse conduction voltage drops. The study provides a quantitative framework for selecting optimal dead times to minimize energy losses, enhancing the efficiency of GaN FET-based inverters in low-voltage motor drive applications. Finally, a dead time optimization strategy is proposed and described.

Effects of Group IVA Elements on the Electrical Response of a Ge2Se3-Based Optically Gated Transistor.

The optically gated transistor (OGT) has been previously demonstrated as a viable selector device for memristor devices, and may enable optical addressing within cross-point arrays. The OGT current-voltage response is similar to a MOSFET device, with light activating the gate instead of voltage. The OGT also provides a naturally built-in compliance current for a series resistive memory element, determined by the incident light intensity on the gate, thus keeping the integrated periphery circuitry size and complexity to a minimum for a memory array. The OGT gate comprises an amorphous Ge2Se3 material that can readily be doped with other elements to alter the transistor's electrical properties. In this work, we explore the operation of the OGT when the Ge2Se3 gate material is doped with the Group IVA elements C, Si, Sn, and Pb. The dopant atoms provide changes to the optical and electrical properties that allow key electrical properties such as the dark current, photocurrent, switching speed, and threshold voltage to be tuned.

Design and Simulation of Bi-Layer Optimized High K- Dielectric Medium for N-Mosfet with Wild Horse Optimization to Improve Electrical Characteristics

Electronic devices for advanced modern semiconductor based technology, mainly focus on the design regarding lighter, faster and more affordable solutions to meet the specifications of modern digital electronics. Some of the drawbacks for minimizing device size in MOSFET include gate insulator scaling, Short-Channel Effects (SCEs), shallow junction technology and off-state leakage current in MOSFET devices. In addition, the traditional SiO2 as a dielectric material contains restricted maximum capacitance as well as increased tunnel current leakage due to the thickness. Hence, a High-k dielectric is required to replace SiO2 to overcome the mentioned issues. In this model, the N-type MOSFET is designed based on the bi-layer high K-dielectric medium with optimized thickness according to the maximum capacitance and minimum threshold voltage, which are implemented on VLSI based applications such as 6 T SRAM for evaluating the performance. The drain current of HfO2, Al2O3 and HfO2+Si3N4 for 2.5 v drain voltage are 1.87 mA, 1.51 mA and 3.54 mA. Then, the read and write delay of the single and bi-layer MOSFET are 70.84 ps, 82.64 ps, 95.21 ps and 10.24 ps, 15.47 ps, 21.74 ps. Thus, the designed and simulated bi-layer optimized high k- dielectric medium for N-MOSFET with wild horse optimization performs better electrical characteristics than the single layer dielectric medium MOSFET.

Study on irradiation effect and damage mechanism in cascode GaN HEMT irradiated by 10 MeV electron

This study investigated the irradiation effect of cascode-structure GaN HEMT (High Electron Mobility Transistor) devices, employing high-energy electrons with an energy of 10 MeV and irradiation doses ranging from 5 to 80 Mrad(Si). The variation of electrical properties of the device under annealing condition was analyzed. Geant4 and TCAD simulations were used to analyze the irradiation effect and damage mechanisms. The results show that the threshold voltage has obvious negative drift and the drain current increases after irradiation. The threshold voltage deviation amplitude of the device increases with the increase of irradiation dose, and the maximum deviation is 1.41V. Annealing at high temperatures (80 °C, 120 °C and 145 °C) partially restores the electrical properties, with a 0.49 V restoration in threshold voltage at 145 °C. Geant4 simulations reveal that enhanced Si MOSFET is more susceptible to total dose effects. TCAD simulations of enhanced Si MOSFET devices demonstrate an increase in electric field intensity, trapped electron concentration, and hole concentration in Si and SiO2 layers with the increase of irradiation dose. These findings can provide support for the space application and irradiation hardening of cascode GaN HEMT devices.

Machine Learning to Promote Efficient Screening of Low-Contact Electrode for 2D Semiconductor Transistor Under Limited Data.

Low-barrier and high-injection electrodes are crucial for high-performance (HP) 2D semiconductor devices. Conventional trial-and-error methodologies for electrode material screening are impractical because of their low efficiency and arbitrary specificity. Although machine learning has emerged as a promising alternative to tackle this problem, its practical application in semiconductor devices is hindered by its substantial data requirements. In this paper, a comprehensive scheme combining an autoencoding regularized adversarial neural network and a feature-adaptive variational active learning algorithm for screening low-contact electrode materials for 2D semiconductor transistors with limited data is proposed. The proposed scheme exhibits exceptional performance by training with only 15% of the total data points, where the mean square errors are 0.17 and 0.27eV for the vertical and lateral Schottky barrier, respectively, and 2.88% for tunneling probability. Further, it exhibits an optimal predictive performance for 100 randomly sampled training datasets, reveals the underlying physical insight based on the identified features, and realizes continual improvement by employing detailed density-of-states descriptors. Finally, the empirical evaluations of the transport characteristics are conducted and verified by constructing MOSFET devices. These findings demonstrate the considerable potential of machine-learning techniques for screening high-efficiency electrode materials and constructing HP 2D semiconductor devices.

A rapid-sintering Cu-Cu joints with ultrahigh shear strength and super reliability for power electronics package

Sintered Cu interconnection technology for power electronics has been widely investigated owing to its unique low temperature sintering high temperature service characteristics and price superiority. However, the currently research usually requires long sintering time (>30 min) and high pressure (>5 MPa). Here, we synthesized copper formate coated Cu nanoparticles (Cu-FA) by a solvothermal reaction, which can achieve rapid sintering at 260 °C with pressure of 5 MPa in 5 min to obtain robust joints of 67.41 MPa for fabricating SiC MOSFET devices. After 1000 h thermal aging and 1000 cycles thermal shock, the strength of joints can still maintained above 50 MPa. Moreover, SiC MOSFET modules were demonstrated using Cu-FA die attachment, which exhibit a 43.6 % lower thermal resistance compared to commercial Sn–Pb solder. Furthermore, copper paste performs better in long-term reliability. This paper provides an effective way to obtain high quality sintered Cu joints rapidly, which is suitable for the packaging of next generation power devices.

Online Temperature Measurement Method for SiC MOSFET Device Based on Gate Pulse

Online Temperature Measurement Method for SiC MOSFET Device Based on Gate Pulse

One-Probe Nanoprobing of Power Devices and Electronic Packages

Results involving the use of a single nanoprobing contact are presented, on both a SiC planar MOSFET device, and a small system-in package. In both cases, mechanical polished samples were prepared, and then probed with a single contact. For the SiC MOSFET, the depletion zones were imaged while the samples were mounted on a 45 ° stub. Discussion of the different signals generated from Passive Voltage Contrast (PVC) and Electron Beam Induced Current (EBIC), as well as possible artifacts of sample grounding, are provided. For the package, Electron Beam Absorbed Current (EBAC) provided indication of connected features within the sample. The experiment showed the capability of measuring features across three orders of magnitude in size.

Enhanced gate biasing resilience in asymmetric and double trench SiC MOSFETs towards generalized highly reliable power electronics

The gate oxide quality in SiC MOSFETs presents a significant challenge, particularly at temperatures exceeding 175 °C. This predicament arises from the gate oxide interface's propensity to trap or release charge carriers, compromising device ruggedness. In mainstream SiC MOSFETs, the gate oxide in the trench corner confronts the demanding task of enduring higher electric field strengths, thereby posing a substantial risk to overall device reliability. As a result, research entities are proactively involved in improving the SiC/oxide interfaces to enhance the devices' resilience against elevated E-field. This endeavor aims to maintain the favorable characteristics of the trench SiC MOSFETs, including low on-state resistance, minimal parasitic capacitance, and exceptional switching performance. Thus, the implementation of a streamlined process becomes crucial to fortify the trench corner, ultimately yielding boosted E-field immunity. In this report, our research focuses on enhancing the reliability of trench corner in SiC MOSFET devices. Specifically, we employ spacer etch technology to selectively shield the trench corner with high-K heterolayers, thereby enhancing the device's ability to withstand higher E-field strengths (59.2 % reinforcement) while mitigating the risk of hidden defects. Importantly, compared to the structure without protection, at high-K shielded layer contact angles ranging from 90 to 150°, the E-field decreases, correlated the enhanced reinforcement at larger angles. Furthermore, such technology enables higher E-fields and greater circuit capacity at the bottom of trench gate, leading to enhanced device reliability. Our studies confirm that the developed device structure exhibits simplicity, reliability, maturity, and controllability, rendering it suitable for large-scale integration applications.

A novel driver circuit of SiC MOSFET for suppressing crosstalk voltage in bridge circuit

Due to the presence of crosstalk voltage in the circuit, SiC MOSFET devices can be damaged or misled. Suppressing crosstalk voltage makes it an important step for the circuit to function properly. This article first delves into the causes of crosstalk voltage generation. The main research object is synchronous Buck converters, and the reasons for the crosstalk voltage of SiC MOSFETs are analyzed. Afterwards, a novel drive circuit was designed to suppress crosstalk voltage, and the working principle of this drive circuit was analyzed. Finally, simulation was conducted using LTspice software to study and analyze the simulation results, proving the feasibility of this novel drive circuit for suppressing crosstalk voltage, and demonstrating the advantages and disadvantages of this novel drive circuit for suppressing crosstalk voltage.

Single Event Effects of Low-Voltage N-type and P-type Trench-gate MOSFET Devices

Single Event Effects of Low-Voltage N-type and P-type Trench-gate MOSFET Devices

A Double-Sided Cooling Approach of Discrete SiC MOSFET Device Based on Press-Pack Package

A Double-Sided Cooling Approach of Discrete SiC MOSFET Device Based on Press-Pack Package

(Invited) Challenges in Fabricating and Scaling up Silicon Carbide Wafers and Devices

Silicon Carbide is rapidly growing in the power electronics industry. This is fueled to a great degree by the adoption of electric cars and power electronics needed both inside the vehicle and to support the charging infrastructure. This attention from automotive industry comes with a clear spotlight on the cost, quality, and efficiency of SiC power devices. This in turn results in intense pressure and scrutiny to improve yields and reduce defects in every part of the manufacturing chain. There is a wide release and proliferation of Diode and MOSFET devices from various companies in the marketplace. Several companies are investing billions of dollars in capacity expansions driving exponential growth of wafers and devices.In this review, we will discuss the steps and processes of fabricating a SiC wafer including crystal growth, wafering, epitaxy and device fabrication. The process challenges associated with the steps unique to SiC will be highlighted with a perspective on scaling up volumes and the transition to 200mm wafers. New innovations at some of the steps are enabling higher efficiency and output. The impact of these innovations will be presented. In addition, defects at each step of the process will be reviewed along with how they interact with the following steps [1]. Finally, the effect of various processes and defects on devices and reliability will be presented [2,3].

Atomic layer deposition mechanism of hafnium dioxide using hafnium precursor with amino ligands and water

As a unique nanofabrication technology, atomic layer deposition (ALD) has been widely used for the preparation of various materials in the fields of microelectronics, energy and catalysis. Hafnium dioxide (HfO2), as an excellent high-κ oxide, is widely used as a substitute gate dielectric for conventional SiO2 in field effect transistor devices. Currently, HfO2 high-κ gate dielectric in MOSFET devices was prepared via ALD technology using tetrakis(dimethylamino)hafnium(IV) (Hf(NMe2)4, TDMAHf) and water (H2O) as the precursors. In this work, the complicated surface reaction mechanism of HfO2 H2O-based ALD using Hf(NMe2)4 was investigated using density functional theory calculations. In the TDMAHf reaction, the dimethylamino group of the precursor was eliminated by ligand exchange reaction with the hydroxyl group on the surface. Subsequently, a second dimethylamino group of TDMAHf could further be eliminated by another hydroxyl group on the surface. In the H2O reaction, ligand exchange reactions and coupling reactions could both occur. By the ligand exchange reactions, water molecule could react with the dimethylamino group on the surface. Simultaneously, the hydroxyl and amino groups could also react with neighboring hydroxyl groups to eliminate dimethylamine and water molecules via the coupling reactions. All these insights into the complicated surface reaction mechanism of H2O-based ALD could promote the further development of ALD chemistry and materials.