MOS Diodes Research Articles

Development of Ge Isotropic Wet Etching Solution and its Application to High Quality Ge-on-Insulator Fabrication through the Etchback Method

Ge has many unique characteristics, such as high carrier mobility and a narrow bandgap corresponding to near-infrared wavelengths. To take advantage of the attractive characteristics of Ge, Ge-on-Insulator (GOI) structures are necessary. In this study, we focus on a direct wafer bonding and etchback method to fabricate GOI structures and explore appropriate etching solutions for the etchback. An HF + H2O2 + CH3COOH solution can isotropically etch Ge and improve surface uniformity. The resulting surfaces were sufficiently flat to achieve Schottky and MOS diodes showing good electrical characteristics of the same level as devices based on commercial mirror-polished Ge surfaces. We discuss the role of the chemicals in the etching solution in achieving the flat surface. We fabricated GOI structures and a back-gate GOI capacitor through direct wafer bonding of SiO2/Si and Al2O3/Ge with the etchback method using the solution. The resulting electrical characteristics are also explained using theoretical calculations. This approach might offer an alternative route to high-quality GOI fabrication.

(Invited) Photo-Assisted Electron Emission from Silicon-Based Electron Emission Devices

Ultrafast pulsed electron sources with spatial coherence have attracted significant interest in emerging applications such as scientific instruments of ultrafast electron microscopy [1-3] and electron beam lithography [4], and also as sources of X-ray [5] and micro- and THz-waves [6-9]. In particular, high-frequency electron bunch trains generated directly from the cathode surface can not only dramatically reduce dimensions and weight through the elimination of the pre-modulation circuit, but can also provide extremely high efficiency and improve the power in the electron beam devices due to coherence effects.One solution is employing photoemission from electron sources driven by ultrashort laser pulses for such emerging applications. Metallic flat photocathodes and recently metallic nanotips have been employed. However, a low quantum efficiency (QE), typically of approximately 0.01 %, and a large work function require a high-power UV laser to generate an intense electron beam. Negative electron affinity (NEA) semiconductor photocathodes such as NEA GaAs can provide QE as high as ~ 10 % [10], operating using visible laser light irradiation. However, the NEA surface is fragile and easily damaged by residual gas adsorption or beam extraction.In this presentation, we introduce the research and development of gated Si-FEAs with a volcano structure and planar-type electron emission devices based on a MOS diode structure and discuss the potential of the devices as a photocathode of the devices operating without NEA surface treatment. We investigate the optical properties of emitted electrons from the devices under visible laser light irradiation. The results indicate that Si-based electron emission devices with a fully optimized structure hold promise as a photocathode with a high QE and a high-speed response for generating a train of ultrashort electron bunches, operating without NEA surface treatment.

Investigation of gap states near conduction band edge in vicinity of interface between Mg-ion-implanted GaN and Al2O3 deposited after ultra-high-pressure annealing

The gap states near the conduction band edge (E C) in the vicinity of the interface between Mg-ion-implanted GaN and Al2O3 deposited after post-implantation annealing were investigated in the range between E C – 0.15 eV and E C – 0.45 eV. For this purpose, capacitance–voltage measurements were performed on MOS diodes with the n-type conduction of Mg-implanted GaN maintained by suppressing the dose. Although the gap state density D T was reduced for the sample prepared with the dose of 1.5 × 1012 cm–2 by conventional rapid thermal annealing (RTA) at 1250 °C for 1 min using an AlN protective cap layer, further improvement was achieved by capless ultra-high-pressure annealing (UHPA) at the same temperature for the same duration. Furthermore, the D T distributions for the samples with capless UHPA at 1400 °C for 5 min are comparable to that for the sample with conventional RTA at 1250 °C for 1 min using the cap layer.

AlGaN/AlN/GaN Metal-Oxide-Semiconductor High-Electron Mobility Transistor with Annealed Al2O3 Gate Dielectric

An AlGaN/AlN/GaN metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMT) with an Al2O3 insulator is studied. The post-deposition annealing (PDA) of Al2O3 is conducted. The effects of PDA in an N2 atmosphere on the performance of the MOS-HEMTs are studied. Experimental results demonstrate that the trap density in the Al2O3 MOS diode is significantly decreased by annealing. Adding annealed Al2O3 as a surface passivation and a gate oxide layer on HEMTs reduces gate leakage currents, increases the two-terminal reverse breakdown voltage, and improves the high-frequency performance of the HEMTs.

A Novel DTSCR With Embedded MOS and Island Diodes for ESD Protection of High-Speed ICs

A novel diode-triggered silicon-controlled rectifier with embedded MOS and island diodes (DTSCR-EMOS-ID) is proposed and investigated. The DTSCR-EMOS-ID was fabricated in 0.18-μm and 22-nm CMOS processes for verifying the process transplantation. The fabricated DTSCR-EMOS-ID presents a low trigger voltage of 1.3 V, a small turn-on resistance of 8 mΩ/μm and a small parasitic capacitance of 43 fF. Meanwhile, the effective failure current and response time of DTSCR-EMOS-ID are optimized to 4.3 A and 3.6 ns, respectively. The DTSCR-EMOS-ID shows much better ESD performance than the conventional LVTSCR and DTSCR fabricated in the same process, which can be attributed to the diode triggering, gate coupling and large injection effects. Moreover, the TCAD simulation results of DTSCR-EMOS-ID agree well with the transmission line pulse testing results, further confirming that the proposed DTSCR-EMOS-ID can be widely used as an effective ESD protection device for high-speed ICs, without the limitation of the fabrication process.

A zero bias highly efficient active diode circuit for piezoelectric energy harvester

This paper presents a MOS based active diode circuit for efficient rectification of piezoelectric energy harvester (PZEH). The active diode consists of a PMOS switch along with auto tuned control circuit to control the gate of the PMOS. The strength of gate voltage of the PMOS in conducting state has been improved to provide the low forward resistance at high current. In the on-state, the voltage drop across the active diode is 33 mV at diode current of 136 µA. The maximum reverse leakage current in the non conduction state of PMOS has been reduced from 18 µA of conventional MOS diode to 1.5 µA. The auto tuned control circuit does not require external bias. The active rectifier using proposed active diode used for ac to dc conversion of PZEH output has been presented in this paper. The circuit provides a power conversion efficiency of 94% which is 36% better than the conventional MOS based rectifier.

Low-temperature annealing behavior of defects in Mg-ion-implanted GaN studied using MOS diodes and monoenergetic positron beam

Mg ions were implanted into Si-doped (5 × 1017 cm–3) n-GaN at a dose of 1.5 × 1011 or 1.5 × 1012 cm–2. MOS diodes were used to characterize the implanted GaN after 300 °C annealing for 3 h and after additional 500 °C annealing for 3 min. Although capacitance–voltage (C–V) characteristics varied with the dosage, the effects of acceptor-like defects induced by ion implantation were observed in the C–V characteristics independently of dosage and annealing temperature. A defect level at approximately 0.25 eV below the conduction band edge was detected electrically. By positron annihilation spectroscopy, its origin was identified as a divacancy consisting of Ga and N vacancies. It was found that its density compared with that of as-implanted GaN decreased with 300 °C annealing, and further increased with 500 °C annealing. This phenomenon was explained on the basis of the difference between the diffusion barriers of possible point defects.

Analysis of simultaneous occurrence of shallow surface Fermi level pinning and deep depletion in MOS diode with Mg-ion-implanted GaN before activation annealing

The characteristics of a MOS diode with Mg-ion-implanted GaN before activation annealing were investigated. Mg ion implantation onto n-GaN with slightly high Si doping concentration (5 × 1017 cm–3) was performed with a moderate dosage (1.5 × 1012 cm–2). The completed MOS diode showed n-type features. The capacitance–voltage (C–V) and capacitance–frequency (C–f) characteristics of the MOS diode indicated that shallow surface Fermi level pinning and deep depletion occurred simultaneously. By applying the conductance method to the measured C–f characteristics, a discrete level at 0.2–0.3 eV below the conduction band edge was detected. On the basis of the simulation of the high-frequency-limit C–V curve, the detected discrete level distributed in the bulk of n-GaN rather than at the insulator/semiconductor interface, so that it caused surface Fermi level pinning at a relatively shallow energy level and deep depletion owing to its acceptorlike nature simultaneously.

CMOS Analog AGC for Biomedical Applications

In this paper, we present the design of an analog Automatic Gain Control with a small silicon area and reduced power consumption using a 0.5 μ m process. The design uses a classical approach implementing the AGC system with simple blocks, such as: peak detector, difference amplifier, four-quadrant multiplier, and inversor amplifier. Those blocks were realized by using a modified Miller type OPAMP, which allows indirect compensation, while the peak detector uses a MOS diode. The AGC design is simulated using the Tanner-Eda environment and Berkeley models BSIM49 of the On-Semiconductor C5 process, and it was fabricated through the MOSIS prototyping service. The AGC system has an operation frequency of around 1 kHz, covering the range of biomedical applications, power consumption of 200 μ W, and the design occupies a silicon area of approximately 508.8 μ m × 317.7 μ m. According to the characteristics obtained at the experimental level (attack and release time), this AGC can be applied to hearing aid systems.

Vital-Sign Processing Receiver With Clutter Elimination Using Servo Feedback Loop for UWB Pulse Radar System

This brief presents a vital-sign processing circuit for simultaneous dc/near-dc elimination and out-of-band interference rejection without any digital signal processing or algorithm assistance for the ultrawideband (UWB) pulse-based radar system. An intrinsic self-balanced MOS diode (SBMD) was proposed as a stable and balanced pseudo resistor applied under a servo feedback loop in a vital-sign receiver of the sensing radar to perform as a high-pass filter (HPF) with an ultralow corner frequency lower than 0.5 Hz for removing undesired clutters of the reflected signals and input dc-offset voltages from innate circuit offsets. A third-order switched-capacitor (SC) Chebyshev low-pass filter (LPF) with leap-frog topology as the subsequent stage was adopted to suppress the out-band noises, thereby establishing an integrated vital-sign processing circuit with bandpass frequency response and incorporating it into a radar module to verify its viability.

Channel Length-Based Comparative Analysis of Temperature and Electrical Characteristics for SiNWT and GeNWT

This paper investigates the temperature sensitivity and electrical characteristics of Silicon Nanowire Transistor (SiNWT) and Germanium Nanowire Transistor (GeNWT) depending on variable channel length (Lg). It also studies the possibility of using them as a temperature nanosensor. The MuGFET simulation tool was exploited to investigate the characteristics of the considered nanowire transistors. Current-voltage characteristics with different values of temperature with channel length [Lg = 25, 45, 65, 85 and 105 nanometer (nm)], were simulated. MOS diode mode connection suggested measuring the temperature sensitivity of SiNWT and GeNWT too. Three (3) electrical characteristics namely; (i) Subthreshold Swing (SS), (ii) Threshold voltage (VT), and (iii) Drain-induced barrier lowering (DIBL) were evaluated and compared for both NWTs. The obtained results show that SiNWT achieved a better temperature sensitivity with channel length range between 25 nm to 105 nm at operation voltage (VDD) range 1 V to 5 V nm. It is very clear that the temperature sensitivity increased remarkably by increasing channel length for both of SiNWT and GeNWT as well, but in SiNWT the sensitivity is more steady compared to GeNWT that showing less sensitivity. Moreover, SiNWT shows better result in terms of electrical performance metrics for various channel length at T = 300 K comparing with GeNWT.

Influence of reactive-ion-etching depth on interface properties in Al2O3/n-GaN MOS diodes

Influence of etching depth on the interface properties in Al2O3/n-GaN MOS diodes has been investigated. The n-GaN surface was etched by inductively coupled reactive-ion-etching (RIE) with shallow (20 nm) and deep etching (1200 nm) depth. The resulting Al2O3/n-GaN interface properties were then evaluated by the capacitance/conductance–voltage (C/G–V) and current–voltage (I–V) characteristics measurements. It was found that: (i) the interface state density of the shallow-etched MOS diode is almost the same as that of the un-etched reference sample, (ii) the deep-etched MOS diode showed around five times higher interface state density than the shallow-etched MOS diode, (iii) the increased interface state density with deep etching was not recovered by Tetra-Methyl-Ammonium Hydroxide (TMAH) treatment nor by post annealing, and (iv) the deep-etched MOS diode indicated about five orders of magnitude higher leakage current, which could be attributed to the lowering of the effective barrier height in the Fowler–Nordheim type conduction. The results obtained in this study indicate that improved RIE process has to be developed for the fabrication of GaN MOS FETs that require deep etching such as vertical trench-type FETs.

Analysis of Deep Level and Oxide Interface Defects Using 100V HF Schottky Diodes and MOS CV for Silicon and 4H SiC HV MOSFETs, Advanced Power Electronics, and RF ASIC

AbstractIn this paper we report high voltage MOS and Schottky Diode CV techniques for silicon and SiC power devices. 4H Silicon carbide is a wide bandgap semiconductor suitable for high voltage power electronics and RF applications due to high avalanche breakdown critical electric field, and thermal conductivity. The performance of various power devices, which may include MOSFET and Static Induction Transistor (SIT), can be affected by the deep level traps in the substrate and the oxide interfacial defects. We have characterized deep level trap (High Voltage Schottky Diode HF CV) and oxide interface trap densities (High Voltage HF MOS CV), measured the device channel doping profile for both 4H SiC and silicon, gate metal workfunction, and simulated the effects on DC/AC performance.

An RF-to-DC Rectifier Based on Tunable Threshold Diodes

This paper proposed a Dickson RF-to-DC rectifier based on floating-gate MOS diodes with tunable threshold voltages to improve RF input sensitivity and to counter process variation in logic CMOS foundry technology. When compensation by active circuits is excluded for system reasons, prior works relied on the availability of diodes with nearly zero threshold voltage in a mixed-signal process, but was unavoidably susceptible to process variation and leakage currents at low thresholds. Our proposed rectifier can have each constituent diode tuned to its optimal threshold at the wafer testing stage to maximize the operational output voltage at various loads and to compensate device-level variations. An optimization algorithm was implemented to automatically take the output voltage as feedback for system calibration in a short duration. The measurements of the tunable-threshold rectifier show > 4dB improvement in input sensitivity compared to the rectifier built by foundry-provided zero-threshold transistors. The proposed circuits can be combined with other techniques including high- ${Q}$ impedance matching for input voltage boosting and hierarchical tandem stages for further improvement on operating conditions. With a ${Q}\,\,{=}$ 10 matching network, −26 dBm sensitivity and 22% efficiency can be achieved for about 0.5 V dc output to a $500~{k} {\Omega }$ load at 570 MHz.

Effect of gate dielectric thicknesses on MOS photodiode performance and electrical properties

Different film thickness was used to investigate the effect of the Al2O3 as a dielectric material for the fabrication of Al/AL2O3/Si/Al MOS diode. Chemical spray pyrolysis method was employed in this work. A high rectification behavior was observed from current-voltage (I-V) measurements in forward and reverse in dark. Optimum ideality factor of (2.36) at 5 sprayed layers was observed, the breakdown voltage found to be 5 MV cm−1 while the barrier height was (0.65 eV) at the same layer thickness. Capacitance-voltage (C–V) measurements was carried out which ensure the formation of abrupt junction; the incorporating built-in potential (Vbi) was estimated and found to be (0.8 eV). In addition, the photodiode shows a good Responsivity of about (1.4, 1.8) Amp/watt at Uv and IR region respectively.

A Compact Model for Border Traps in Lateral MOS Devices with Large Channel Resistance

In this letter, a distributed network model describing the effects of the border traps and distributed channel resistance on the impedance frequency dispersion of lateral MOS devices is proposed. The proposed model is verified using a gate recessed, normally-off Al2O3/GaN MOSFET structure operating as a MOS diode. The measured frequency-dependent capacitance and conductance curves of the MOS diode over a wide frequency range are found to be in good agreement with the proposed model. According to the intrinsic property of border traps to the ac signal, the proposed model is further modified to get the spatial distribution of border traps. The new insight derived from the impedance dispersion characteristics of lateral MOS devices is critical for quantitative analysis of the quality of III-V lateral MOS structures.

Impact of low-temperature annealing on defect levels generated by Mg-ion-implanted GaN

The impact of low-temperature annealing on Mg-ion-implanted GaN with a low dosage (1.5 × 1011 cm−2) has been investigated using MOS diodes. Low-temperature annealing was carried out for Mg-ion-implanted GaN in the temperature range from 400 °C to 700 °C before forming the insulator/semiconductor interface of the tested MOS diodes. Upon annealing, the hysteresis and the slope of the capacitance–voltage (C–V) curves, which were affected by deep levels in the GaN bulk, were changed with the annealing temperature. In particular, the shape of C–V curve was changed by annealing at a temperature as low as 500 °C. The C–V curves were found to be reproducible by a simulation in which the dominant deep levels were assumed to be located at 0.1 and 0.7 eV below the conduction band edge. Considering the low recovery temperature and low dosage, the possibility of the existence of simple defects after implantation is discussed.

High temperature current transport in gate oxides based (GaN)/AlGaN/GaN Schottky diodes

We have prepared high temperature stable Schottky MOS diodes on AlGaN/GaN heterostructure with Ir-Al oxide based gate oxide layer and analyzed current transport mechanism in these diodes up to very high temperatures. The thermionic emission analysis of I-V curves gave high ideality factor in between 2 and 3 decreasing with increasing temperature. Simulation of the thermionic transport with the barrier height extracted from the measured curves and ideality factor unity gave the simulated current densities many orders of magnitude higher than experimentally measured. We explained experimental data by a bias dependent barrier height as a result of thin dielectric layer and a bias dependent charge localized in interface traps between the semiconductor and this dielectric layer. The measured data are then explained by the thin dielectric layer at the interface between (GaN)AlGaN and the metal electrode. Increasing forward voltage and moving Fermi level towards conduction band the charge in the traps becomes negative and increases the effective barrier height for electrons moving from the semiconductor into the metal. By this mechanism also a linear increase of reverse current with bias can be explained. The opposite is true for the reverse voltage.

Total Dose Effects on Voltage References in 130-nm CMOS Technology

This paper investigates the impact of total ionizing dose (TID) effects on the performance of CMOS voltage reference circuits. Four circuits were designed using a commercial 130-nm CMOS process and without any radiation-hardening technique. Two of the designed circuits generate the output voltage proportional to the bandgap voltage, while the other two generate the output voltage proportional to the MOS threshold voltage. The measured output voltage variation caused by TID was from 1% to 15% for a total dose of up to 500 krad, depending on the circuit topology. The leakage currents induced by radiation in MOS transistors and diodes were the main cause of output voltage variation.

(Invited) Rectifiers, Mos Diodes and LEDs Made of Fully Porous GaN Produced by Chemical Vapor Deposition

GaN is an important wide band-gap semiconductor in electronics and optoelectronics. In its porous form is particularly interesting for developing optoelectronic devices with improved efficiency, such as LEDs with enhanced efficiency and sensors with enhanced sensitivity. Through chemical vapour deposition (CVD) [1], we have shown that it is possible to produce nanoporous GaN without any etching or chemical post-growth treatment, with the porosity being present only on the (0001) face of the material. Low resistivity ohmic Pt and Au metallic contacts were demonstrated on porous n-type GaN by the formation of intermetallic seed layers through the vapour-solid-solid (VSS) mechanism [2]. Also, we have been able to develop p-type porous GaN by doping with Mg, with a charge carrier concentration of the order of 1018 cm-3 [3]. By tuning the concentration of Mg, introduced as Mg2N3 in the CVD system, it has been possible to form a polycrystalline high-k oxide between an ohmic metallic alloy interlayer contact and the porous GaN, while maintaining a clean interface, that allowed to fabricate a MOS-type diode on silicon in a single growth regime [4]. Through the careful selection of the substrate it has also been possible to produce porous GaN epitaxial layers [5] that allow for the fabrication of high quality partially and fully porous GaN rectifying p-n junctions, through a two step CVD process, and show their behaviour as diodes with effective uniform conduction under a green technology [6]. Here, we will also present the recent results we obtained in the light emission of these structures. Thus, these porous junctions have potential applications in high brightness unencapsulated LEDs with enhanced light emitting properties and high surface area sensors with improved sensitivity. [1] Carvajal & Rojo, Crystal Growth Des., 9 (2009) 320 [2] Bilousov et al., ACS Appl. Mater. Interfaces 4 (2012) 6927 [3] Bilousov et al., Appl. Phys. Lett. 103 (2013) 112103 [4] Bilousov et al., Chem. Mater. 26 (2014) 1243 [5] Bilousov et al., CrystEngComm 16 (2014) 10255; Bilousov et al., ACS Appl. Mater. Interfaces 6 (2014) 17954 [6] Carvajal et al., ECS Transactions 66 (2015) 163 Figure 1