MOS Diodes Research Articles

(Invited) Rectifiers, Mos Diodes and LEDs Made of Fully Porous GaN Produced by Chemical Vapor Deposition

We reviewed the work done in recent years about porous GaN produced by chemical vapor deposition (CVD) that allowed demonstrating p-n junction rectifiers and MOS diodes in a simple manner and without involving post-growth steps to induce porosity. p-n junction rectifiers exhibited stable rectification in the range ±1-±5 V, with very stable values of current with time. MOS diodes were fabricated in a single growth step formed by a MgO dielectric interlayer in between Mg-doped porous GaN and a Mg-Ga metallic alloy. Finally, we present the fabrication of LEDs based on this porous material. Despite the high resistivity, that induced a turn on voltage of ~13 V, the emission consisted only in one peak centered at 542 nm. Our porous GaN films exhibit random porosity when compared to arrays of nanostructures, however, their easy deposition over large areas without dominating leakage currents is promising for wideband gap applications.

Investigation of FinFET as a Temperature Nano-Sensor Based on Channel Semiconductor Type

This paper represents the temperature effect on FinFET transistor and the possibility of using it as a temperature nano-sensor. The MuGFET simulation tool was used to investigate temperature characteristics of the FinFET. Current-voltage characteristics with different values of temperature were simulated. MOS diode connection suggested using the FinFET transistor as a temperature nano-sensor. The final results shows that the best FinFET used as a nano- sensor is with GaAs because it has the greatest ΔΙ (=10.9%) referring to ΔΙ at 25°C, and the best FinFET stable with increasing working temperature is Si-FinFET because it has the lowest ΔΙ (=6%) referring to ΔΙ at 25°C.

Rectifiers, MOS Diodes and LEDs Made of Fully Porous GaN Produced by Chemical Vapor Deposition

Here we present the fabrication of LEDs based on porous GaN produced by chemical vapor deposition (CVD) and reviewed the work done that allowed demonstrating p-n junction rectifiers and MOS diodes in a simple manner and without involving post-growth steps to induce porosity. p-n junction rectifiers exhibited stable rectification in the range ±1–±5 V, with very stable values of current with time. MOS diodes were fabricated in a single growth step formed by a MgO dielectric interlayer in between Mg-doped porous GaN and a Mg-Ga metallic alloy. Despite the high resistivity observed in the LEDs fabricated, that induced a turn on voltage of ∼13 V, the emission consisted only in one peak centered at 542 nm. Our porous GaN films exhibit random porosity when compared to arrays of nanostructures, however, their easy deposition over large areas without dominating leakage currents is promising for wideband gap applications.

A study of the electrical properties of self-biased channel MOS diodes for solar-cell applications

AbstractWe propose two types of low-cost, low-loss diodes as alternatives to Schottky barrier diodes (SBDs) for use as bypass diodes connected in parallel with solar-cell panels. Both of our proposed devices are self-biasing channel MOS diodes consisting of an n-channel MOS structure that features three-terminal operation combined with a DMOS cell structure exploiting self-biasing effects. By reducing the threshold voltage of the MOS gate, these devices feature lower on-voltages and lower rates of growth in the reverse leakage current with increasing temperature, thus preventing thermal runaway. To investigate the properties of our devices, we used a device simulator to analyze their performance as bypass diodes for a solar-cell panel. Our results indicate that when a shadow partially covers the cell, the current flowing on the load side of the solar-cell panel is about 50% larger than that observed for a Cr SBD, indicating the potential for significantly improved performance.

Thermal Assessment of AlGaN/GaN MOS-HEMTs on Si Substrate Using Gd2O3 as Gate Dielectric

Thermal stability of AlGaN/GaN metal–oxide–semiconductor high-electron mobility transistors (MOS-HEMTs) and diodes using Gd2O3 is investigated by means of different thermal tests. DC and pulsed $I$ – $V$ characterization of the devices before and after the processes shows that the devices with Gd2O3 dielectric layer have more than three orders of magnitude lower leakage current, higher ON/OFF ratio of about $10^{8}$ , and better thermal stability after the long thermal storage test (500 °C, 8 days) compared with conventional devices. In addition, no hysteresis and a stable threshold voltage were observed after a short thermal test (500 °C, 5 min) in the MOS diodes, in good agreement with the lower trapping effects observed in the MOS-HEMTs.

Design of Voltage Multipliers for Maximized DC Generation in Inductively Coupled RFID Tags

This paper presents models, circuit solutions and design procedures for maximized DC generation in inductively coupled RFID tags. An analytical model for the DC generation is derived, and relationships between the received signal in the tag coil antenna and the generated DC supply voltage using a voltage multiplier, based on both passive and active diodes, are presented. Derived from the trade-off between voltage gain in the multiplier and the tag coil at resonance, an equation for the optimum number of multiplier stages to achieve maximized DC generation is presented. Based on the derived equation, design examples are included with two typical tag coil antennas given a specification of the DC supply voltage and current. Also included in this paper is the design of a voltage multiplier based on active diodes implemented and manufactured in AMS 0.35 μm CMOS process. The active diodes are based on a concept of threshold cancellation of MOS diodes and make use of reverse leakage control to achieve full threshold cancellation.

Investigation of Temperature-Dependent Characteristics of AlGaN/GaN MOS-HEMT by Using Hydrogen Peroxide Oxidation Technique

This paper investigates the temperature-dependent performances of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT). The gate dielectric layer and surface passivation layer are formed by the H 2 O 2 oxidation technique. The gate dielectric quality is estimated by the breakdown electric field (EBD) and low-frequency noise. The capacitance-voltage (C-V) hysteresis characteristics of MOS and Schottky diodes at 300/480 K are also studied. An appropriate thermal model is used to investigate the self-heating effect and calculate the effective channel temperature (T eff ). The dc performances of the present MOS-HEMT are improved at 300/480 K, as compared with a Schottky-barrier HEMT (SB-HEMT), including output current density, maximum extrinsic transconductance (gm,max), gate voltage swing, gate-drain leakage current (IGD), specific ON-resistance (RON), three-terminal OFF-state breakdown voltage (BVOFF), and subthreshold swing. Factors that cause IGD and BVOFF are analyzed by the temperature-dependent measurement. The passivation effect of the present MOS-HEMT is also confirmed by the surface leakage measurement. The devised MOS-HEMT demonstrates superior thermal stability to the reference SB-HEMT. The present-design is promising for high-temperature electronic applications.

Electrical properties of MOS diodes In/TiO2/p-CdTe

In/TiO2/p-CdTe MOS diodes, which have a rectification coefficient of K = 6 × 103 at an external bias of 2 V, are fabricated for the first time by means of the inexpensive spray-pyrolysis method. It is established that tunnel-recombination processes in the MOS structures under investigation for forward and reverse voltages with the participation of levels at an energy depth of 0.25 eV are the dominant current-flow mechanism. The features of the voltage-capacitance characteristics of In/TiO2/p-CdTe MOS diodes testify to a sharp decrease in the resistance of the TiO2 high-resistance layer at forward bias, which is caused by the relation between the energy parameters of components of the MOS structure under investigation.

Co-Design of a CMOS Rectifier and Small Loop Antenna for Highly Sensitive RF Energy Harvesters

In this paper, a design method for the co-design and integration of a CMOS rectifier and small loop antenna is described. In order to improve the sensitivity, the antenna-rectifier interface is analyzed as it plays a crucial role in the co-design optimization. Subsequently, a 5-stage cross-connected differential rectifier with a 7-bit binary-weighted capacitor bank is designed and fabricated in standard 90 nm CMOS technology. The rectifier is brought at resonance with a high-Q loop antenna by means of a control loop that compensates for any variation at the antenna-rectifier interface and passively boosts the antenna voltage to enhance the sensitivity. A complementary MOS diode is proposed to improve the harvester's ability to store and hold energy over a long period of time during which there is insufficient power for rectification. The chip is ESD protected and integrated on a compact loop antenna. Measurements in an anechoic chamber at 868 MHz demonstrate a -27 dBm sensitivity for 1 V output across a capacitive load and 27 meter range for a 1.78 W RF source in an office corridor. The end-to-end power conversion efficiency equals 40% at -17 dBm.

Porous GaN and High-κ MgO–GaN MOS Diode Layers Grown in a Single Step on Silicon

Porous GaN polycrystalline layers with n-type conduction characteristics were catalytically grown from Mg films formed by decomposition of a Mg2N3 precursor typically employed for activating p-type conduction in GaN. After being exposed to oxygen, the Mg film oxidized to a polycrystalline high-κ oxide between the ohmic alloy interlayer contact and the porous GaN, while maintaining a clean interface. Electrical measurements on devices coupled to composition analysis and electron microscopy of the component layers confirm that a MOS-type porous GaN diode on silicon can be formed by chemical vapor deposition in a single growth regime.

Running on starlight

Researchers at the University of Hyogo, Japan, are working on using the field effect of MOS diodes to increase the amount of energy solar cells extract from sunlight. The results of their research into these structures so far lead the team to believe that the MOS gated-TFSC will be a useful addition to solar cell technology, as interest in `green' ambient power sources for consumer electronics increases.

Interfacial band configuration and electrical properties of LaAlO3/Al2O3/hydrogenated-diamond metal-oxide-semiconductor field effect transistors

In order to search a gate dielectric with high permittivity on hydrogenated-diamond (H-diamond), LaAlO3 films with thin Al2O3 buffer layers are fabricated on the H-diamond epilayers by sputtering-deposition (SD) and atomic layer deposition (ALD) techniques, respectively. Interfacial band configuration and electrical properties of the SD-LaAlO3/ALD-Al2O3/H-diamond metal-oxide-semiconductor field effect transistors (MOSFETs) with gate lengths of 10, 20, and 30 μm have been investigated. The valence and conduction band offsets of the SD-LaAlO3/ALD-Al2O3 structure are measured by X-ray photoelectron spectroscopy to be 1.1 ± 0.2 and 1.6 ± 0.2 eV, respectively. The valence band discontinuity between H-diamond and LaAlO3 is evaluated to be 4.0 ± 0.2 eV, showing that the MOS structure acts as the gate which controls a hole carrier density. The leakage current density of the SD-LaAlO3/ALD-Al2O3/H-diamond MOS diode is smaller than 10−8 A cm−2 at gate bias from −4 to 2 V. The capacitance-voltage curve in the depletion mode shows sharp dependence, small flat band voltage, and small hysteresis shift, which implies low positive and trapped charge densities. The MOSFETs show p-type channel and complete normally off characteristics with threshold voltages changing from −3.6 ± 0.1 to −5.0 ± 0.1 V dependent on the gate length. The drain current maximum and the extrinsic transconductance of the MOSFET with gate length of 10 μm are −7.5 mA mm−1 and 2.3 ± 0.1 mS mm−1, respectively. The enhancement mode SD-LaAlO3/ALD-Al2O3/H-diamond MOSFET is concluded to be suitable for the applications of high power and high frequency electrical devices.

Nano-Crystalline Silicon-Based Bottom Gate Thin-Film Transistor Grown by LTPECVD With Hydrogen-Free He Diluted ${\hbox{SiH}} _{4}$

The bottom-gate nc-Si based thin-film-transistors (TFTs) grown by using the low-temperature plasma-enhanced chemical vapor deposition (LT-PECVD) system with He diluted SiH are demonstrated. With the RF plasma power increasing from 20 to 100 W, the crystalline volume ratio of the nc-Si inside the a-Si:H film significantly increases from 12.5% to 32%, and its deposition rate is also enhanced from 9.5 to 14.5 nm/min. The faster deposition at higher plasma greatly suppresses the residual oxygen content in nc-Si film to 4% or less, which reduces the flat-band shifted voltage of the MOS diode by 2 volts. The increased crystalline volume with suppressed oxide in nc-Si films contribute to the enhanced Hall mobility and conductivity. The nc:Si TFT decreases its threshold voltage from 3.3 V to 2.7 V, and enlarges its field mobility from 0.3 to 1.3 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V-s. The defect density in the nc-Si TFTs further decrease by one order of magnitude to 7.5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">16</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> eV, which causes a shrinkage on the sub-threshold operation range to make easier the operation of the nc-Si TFTs entering into the above-threshold regime at lower voltage. The hydrogen-free He diluted SiH growth has shown its compatibility with the conventional recipe for the high-mobility nc-Si TFT fabrication.

Improvement of the electrical properties of Al2O3/AlGaN/GaN MOSHFETs by gate‐first process

AbstractWe have studied “gate‐first process” in the fabrication of the Al2O3/AlGaN/GaN metal‐oxide‐semiconductor heterostructure field‐effect transistors (MOSHFETs) to improve the electrical properties of the MOSHFETs, where Al2O3 gate oxide is deposited before ohmic contact alloying. The interface state density of the Al2O3/GaN MOS diodes fabricated by the gate‐first process was more than one order of magnitude smaller than that of the diodes fabricated by the conventional “gate‐last process” where Al2O3 gate oxide was deposited after ohmic contact alloying. In addition, the saturation of the drain current at large gate voltages in the ID‐VGS characteristics of the Al2O3/AlGaN/GaN MOSHFETs was relaxed and the maximum drain current was increased by employing the gate‐first process. The hysteresis width of the ID‐VGS curve of the MOSHFETs fabricated by the gate‐first process was smaller than that of the devices fabricated by the gate‐last process. (© 2013 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Metal-oxide-semiconductor diodes containing C60 fullerenes for non-volatile memory applications

For non-volatile memories, silicon-oxide-nitride-oxide-silicon or floating gate structures are used to store information by charging and discharging electronic states reversibly. In this article, we propose to replace the floating gate by C60 molecules. This would allow more defined programming voltages because of the discrete molecular energy levels and a higher resistance to tunneling oxide defects because of the weak electrical connection between the single molecules. Such C60 MOS diode structures are produced and their electrical properties are analyzed regarding current transport and charging mechanism of the molecules. To create the MOS structures, C60 molecules (5% of a monolayer) are evaporated onto a part of a clean silicon wafer and covered by amorphous silicon in situ in an ultra high vacuum system. Then the wafer is oxidized in wet atmosphere at just 710 °C through the C60 layer. The goal is to produce a clean oxide above and under the molecules without destroying them. Aluminum gate contacts are defined on top of these layers to perform complementary capacitance voltage (CV) and current voltage (IV) measurements. First, the gate voltage is swept to analyze the injection current, then CV measurements are performed after each sweep to analyze the charge state of the C60 layer and the oxide quality. Reference diodes without C60 on the same wafer show an identical Fowler-Nordheim (FN) tunneling behavior for currents injected from silicon or from aluminum, respectively. In the CV curves, no pronounced flatband voltage shift is observable. In diodes with C60, for negative gate voltages, a classical FN tunneling is observed and compared to theory. The electron injection from silicon shows a different tunneling current behavior. It starts at a lower electric field and has a smaller slope then a FN current would have. It is identified as a trap-assisted tunneling (TAT) current caused by oxidation-induced traps under the C60 layer. It is modeled by an established analytic TAT model which reproduces the data with a trap energy of 1.8 eV below the oxide conduction band. In the CV measurements the negative voltage IV sweeps result in a shift of the flatband voltages to more negative values. Positive voltage IV sweeps shift the CV curves back onto the starting curves. This proves positive charge trapping in the oxide which results in a non-volatile memory behavior for the diodes with C60.

Conduction Mechanism Analysis of Inversion Current in MOS Tunnel Diodes

Self inversion issue and excess capacitance phenomenon were observed for the first time in relatively thick silicon dioxide (SiO2) in the form of MOS (metal(Al)/SiO2/p type crystalline silicon) structure. Both phenomena were based on minority carriers (electrons in this case) and studied through DC current-applied bias voltage (I-V) and AC admittance measurements in dark/light condition as a function of ambient temperature (295 - 380 K). Either of the cases was the departure of traditional MOS analysis, manifesting themselves in the inversion regime of MOS diode. Increase in frequency/temperature/light intensity within dark and light conditions led to weaken the maxima of hump in C-V curves and finally turned into deep depletion mode after exceeding threshold value of frequency/temperature/light intensity. In resumed conditions, supplementary I-V measurements were carried out to describe the generation and conduction mechanism(s) for minority carriers (electrons).

A Model for MOS Diodes With $V_{\rm th}$ Cancellation in RFID Rectifiers

A theoretical model for diode-connected MOS transistors with a threshold cancellation technique is developed. The model is based on a detailed analysis of the technique with internal threshold cancellation (ITC) and reveals design insight and performance limitations. Derived design equations illustrate the tradeoff between the voltage drop and the reverse leakage of the diode. Furthermore, a design procedure for the optimization of the power conversion efficiency (PCE) of a bridge rectifier with ITC MOS diodes was developed based on the model. A rectifier was designed and implemented in an austriamicrosystems 0.35-μm CMOS process, and Cadence simulation results of the PCE and the voltage conversion efficiency show good agreement with the model.

Influence of Threading Dislocations on Lifetime of Gate Thermal Oxide

The reliability of gate oxides is a fundamental issue for realizing SiC MOSFETs. Many reports said that crystal defects shorten the lifetime of the gate oxide. And, epi defects, the basal plane dislocations and threading screw dislocations (TSD) are considered killer defects. However, because of the high TSD density of commercial SiC wafers, the exact relationship between other kinds of dislocations with lifetime has not been revealed. On the other hand, RAF wafers that we developed have low TSD density, so it is easy to evaluate the relationship between other kinds of dislocations and lifetime. By using RAF wafers, in this study, we clarified the relationship between the lifetime of the gate oxide and crystal defects. We fabricated MOS diodes and measured their lifetimes by TDDB (Time Dependent Dielectric Breakdown) measurement. The breakdown points were defined by the photo-emission method. Finally, we classified the defects by TEM (Transmission Electron Microscopy). As the results, it was clarified that threading edge dislocation (TED) decreases the lifetime as does TSD, which earlier reports said. The lifetime of the gate oxide area, in which a TED is included, was shorter by one order of magnitude than a wear-out breakdown. And, the TSD was two orders.

Characterization of Al2O3/InSb/Si MOS diodes having various InSb thicknesses grown on Si(1 1 1) substrates

This paper discusses the capacitance–voltage (C–V) characteristics of Al2O3/InSb/Si (1 1 1) MOS diodes grown using MBE via InSb bi-layer with special care to the surface reconstruction. This growth technique is based on our finding that the InSb layer grown on a Si (1 1 1) substrate is rotated by 30° with respect to the substrate under certain initial conditions. This rotation drastically reduces the lattice mismatch from 19.3% to 3.3%, and improves the crystal quality of an InSb layer. To investigate the possibilities of InSb MOSFETs on Si substrates, we fabricated MOS diodes having an Al2O3 insulator film deposited by atomic layer deposition. C–V characteristics were measured both at RT and 77 K. It was found that the InSb grown on Si shows a degraded C–V curve compared to the InSb substrate, even though the mobility of the grown layer is quite high. We also investigated the effects of InSb thickness on the C–V characteristics of the MOSFETs. It was found that the quality of MOS diodes first degrades when decreasing the InSb thickness from 1 μm to 50 nm; further reduction of the InSb thickness improves it again. It was demonstrated that the MOS diode having a 10 nm InSb layer shows a good C–V curve, which is comparable to that of the InSb substrate. Finally, we discussed the possibility of the InSb/Si pseudomorphic MOSFETs.

Damage Efficiency Research of PCB Components under Strong Electromagnetic Pulse

To study damage effectiveness of strong electro-magnetic pulse to components of equipments, the power density in area of MOS circuit, diodes and transistor of a computer is simulated, using the method of the finite-difference time-domain (FDTD). Coupling laws in different areas are achieved, and then judging the damage efficiency of components. Electromagnetic pulse reflects constantly in computer box, causing power density appears oscillations. Energy gradually declines to zero, for it radiates outward from slots. Field concentration around PCB board results in dissociation of field strength, and slows down the attenuation of energy. Finally, formula of power density at random field strength and rise time is also obtained.