MOS Diodes Research Articles

Electrical Performance of Chlorine-Treated AlGaN MOS Diodes with i-ZnO Insulator

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Solvent dependency of pentacene degradation for top-gate-type organic ferroelectric memory

To minimize the degradation of pentacene films in the fabrication of top-gate-type MFS FETs (metal-ferroelectric-semiconductor field-effect transistors), the characteristics of four solvents which are used for overcoating organic ferroelectric films on pentacene films are investigated by dipping pentacene MOS diodes in these solvents. Then, using appropriate solvents such as 1,4-dioxane, MFS diodes composed of Au, P(VDF-TrFE) (poly(vinylidene fluoride-trifluoroethylene)), and pentacene are fabricated, and then C– V (capacitance vs. voltage) characteristics are investigated. It is concluded from comparison of C– V and data retention characteristics of the top- and bottom-gate-type MFS diodes that degradation of the pentacene film is insignificant when an appropriate solvent is used.

Some Issues of Modeling the Double Barrier Metal-Oxide-Semiconductor Tunnel Structures

The paper discusses some issues of modeling the MOS tunnel structure with a gate stack containing a semiconductor quantum well (double barrier MOS system). The considerations are illustrated by simulations with the use of a theoretical model. Results of simulations are compared with experimental characteristics of fabricated DB MOS diodes.

Fully-Automated and Portable Design Methodology for Optimal Sizing of Energy-Efficient CMOS Voltage Rectifiers

This paper presents a specific, fully-automated and portable design methodology used to optimize implementations of AC-DC rectifiers using MOS diodes. Output voltage and efficiency are theoretically analyzed taking into account influences of devices DC and AC characteristics, input signal voltages and frequencies as well as load currents, temperatures, backgate voltages and even capacitors and diodes parasitic capacitances. An experimental voltage multiplier is designed in a 1 μm multiple-threshold voltage SOI CMOS technology for ultra low power applications at 13.56 MHz .

Determination of hole effective mass in SiO2 and SiC conduction band offset using Fowler–Nordheim tunneling characteristics across metal-oxide-semiconductor structures after applying oxide field corrections

Fowler–Nordheim electron and hole tunneling characteristics across 4H-SiC MOS diodes are studied. Their slope constants are used to determine the hole effective mass in the thermal SiO2 and the 4H-SiC conduction band offset. The hole effective mass in the SiO2 is found to be 0.58 m, where m is the free electron mass. The 4H-SiC conduction band offset is found to be 2.78 eV. The average oxide fields used in the carrier tunneling characteristics are formulated. It is found that anode and cathode field corrections by the flatband voltage are critical in the evaluation of the above tunneling parameters.

Comparative study of AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors with Al 2O 3 and HfO 2 gate oxide

AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors (MOSHFETs) with Al 2O 3 gate oxide which was deposited by atomic layer deposition (ALD) were fabricated and their performance was then compared with that of AlGaN/GaN MOSHFETs with HfO 2 gate oxide. The capacitance ( C)–voltage ( V) curve of the Al 2O 3/GaN MOS diodes showed a lower hysteresis and lower interface state density than the C– V curve of the HfO 2/GaN diodes, indicating better quality of the Al 2O 3/GaN interface. The saturation of drain current in the I D– V GS relation of the Al 2O 3 AlGaN/GaN MOSHFETs was not as pronounced as that of the HfO 2 AlGaN/GaN MOSHFETs. The gate leakage current of the Al 2O 3 MOSHFET was five to eight orders of magnitude smaller than that of the HfO 2 MOSHFETs.

Selective etching of HfN gate electrode for HfN/HfSiON gate stack in-situ formations

In order to fabricate metal gate/high-k gate stacks utilizing ECR sputtering, selective etching of HfN gate electrodes was investigated. It was found that etching rates of HfN gate electrodes at room temperature were 2.9 and 0.23nm/s for DHF (1%) and the mixed solution of HF:H2O2:H2O = 1:2:40, respectively. In addition, the etching selectivity for HfN/HfSiON was relatively high, such as the ratio of 65 which was 3 times higher than that of DHF (1%) by the mixed solution. After the in-situ formation of HfN/HfSiON layers on p-Si(100) and post deposition annealing (PDA), pattering of HfN was carried out utilizing the selective etching process. In case the PDA of 800°C/15s, the MOS diodes were found to be successfully fabricated, and the equivalent oxide thickness (EOT) of 0.56nm, and the leakage current at VFB-1 V of 1.3A/cm2 were obtained.

Investigation of n-Type Pentacene Based MOS Diodes with Ultra-Thin Metal Interface Layer

In order to realize stable n-type characteristics of pentacene for applying to the organic complementary metal-oxide-semiconductor field-effect transistors (CMOS), we have fabricated pentacene based MOS diodes using ultra-thin Yb layer such as 0.5-3nm between gate insulator and pentacene. From the results of capacitance-voltage (C-V) measurements, excellent n-type C-V characteristics of the devices with 1 and 2nm-thick Yb were observed even though the devices were measured in air. These results suggested that the n-type semiconductor characteristics of pentacene are able to be improved by the thin Yb interfacial layer. Furthermore, the improved n-type characteristics of pentacene will enable the fabrication of flexible complementary logic circuits utilizing one kind organic semiconductor.

Analysis of a bipolar energy-transport model for a metal-oxide-semiconductor diode

A simplified bipolar energy-transport model for a metal-oxide-semiconductor diode (MOS) with nonconstant lattice temperature is considered. The electron and hole current densities vanish in the diode but the particle temperature may be large. The existence of weak solutions to the system of quasilinear elliptic equations with nonlinear boundary conditions is proved using a Stampacchia trunction technique and maximum principle arguments. Further, an asymptotic analysis for the one-dimensional MOS diode is presented, which shows that only the boundary temperature influences the capacitance–voltage characteristics of the device. The analytical results are underlined by numerical experiments.

Si Nano-Dots and Nano-Pyramids Dependent Light Emission and Charge Accumulation in ITO/SiO$_{\rm x}$/p-Si MOS Diode

The current blocking and charge accumulation effects of an ITO/Si-rich SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /p-Si MOS diode with buried Si nano-dots and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Si interfacial Si nano-pyramids are characterized. The ITO/Si-rich SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /p-Si MOS diodes exhibits the 3.5 ± 0.2 nm large Si nano-dots with volume density of 4-5×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> . At the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /p-Si interface, the area density of Si nano-pyramids is increasing from 1.3×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> to 1.6×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , which greatly decreases turn-on voltage of the MOS diode from 182 to 52 V, thus enhancing the electro-luminescent power from 17.5 to 50.4 nW. The current blocking phenomenon of such a MOS diode become serious with lengthening step-voltage delay, indicating that a significant charge accumulation associated with a strong screening field is generated within Si-rich SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> layer. It was observed that the turn-on voltage with Si nano-pyramids evidently decreases to 31.6 V under reverse biased conditions for tunneling holes. Counter-clockwise C-V hysteresis analysis reveals a flat-band voltage shift of 8.5 V for electron and -12.9 V for hole, showing nonlinear function with either Si nano-dot volume or density. The C-t retention shows higher charge loss rate for electrons (7.6%) than for holes (1.5%) within 0.5 hr due to low SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Si nano-dot barrier.

10.1007/s11453-008-3017-2

Experimental data on the dependence of the flat-band voltage and relaxation time for the capacitance of the space-charge region in an MOS diode (Pd-SiO2-n-Si) on the hydrogen concentration in a hydrogen/air gaseous mixture are discussed. It is assumed that variation in the flat-band voltage U fb in an MOS structure with the thickness d = 369 nm subjected to a hydrogen/air gaseous mixture can be accounted for by the formation of dipoles in the Pd-SiO2 gap due to polarization of hydrogen atoms (H a ). An analytical expression describing the dependence of variation in the flat-band voltage ΔU fb on the hydrogen concentration $$ n_{H_2 } $$ was derived. In MOS structures with d ≤ 4 nm (or MOS diodes), the value of ΔU fb is mainly controlled by passivation of the centers responsible for the presence of the surface acceptor-type centers at the SiO2-n-Si interface by hydrogen atoms. Analytical expressions describing the dependences of ΔU fb and the capacitance relaxation time in the space-charge region on $$ n_{H_2 } $$ are derived. The values of the density of adsorption centers and the adsorption heat for hydrogen atoms at the Pd-SiO2 and SiO2-n-Si interfaces are found.

Thermal oxidation of lattice matched InAlN/GaN heterostructures

AbstractIn this work we have investigated the thermal oxidation of thin InAlN/GaN heterostructures in their lattice matched configuration (83% Al) in oxygen atmosphere at 800 °C. TEM cross sections revealed a partially crystalline oxide with an initial oxidation rate of 0.37 nm/minute. MOS diodes fabricated using the thermal oxide as a gate dielectric showed an exponential drop in the gate leakage which scales with the square root of oxidation time indicating diffusion limited oxidation through the InAlN barrier. The effect of oxidation on the interfacial InAlN/GaN sheet charge density (NS) is correlated with a reduction of thickness for short oxidation times (up to 4 min) and an abrupt change in the surface potential for longer oxidation times. (© 2010 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Analysis and Modeling of Leakage Current for Four-Terminal MOSFET in Off-State and Low Leakage Switches

Leakage current for MOSFET in off-state is one of the serious problems in charge-based analog circuits under low power supply. To suppress the leakage current, a method that a slight voltage is applied to source to accomplish reverse bias between source and bulk is proposed. The proposed bias condition, also other bias conditions, is analyzed by injection carrier density in p-n junction and surface carrier concentration in MOS diode in four-terminal MOSFET. Leakage current is modeled by combining the characteristics of p-n junction with MOS diode in MOSFET. The characteristics of MOSFET fabricated with a standard 0.18µm n-well CMOS technology are measured to investigate the basic principle. Measured leakage current fits to the theoretical leakage current exactly. The proposed slight bias to source terminal in MOSFET is proved most efficient to reduce the leakage current. Based on the proposed source bias condition, MOSFET switches with low leakage current under a single power supply are proposed.

PTAT Voltage Generator under Ultra Low Power Supply with Two Subthreshold MOSFETs between Rails

A proportional to absolute temperature voltage (PTAT Voltage) generator under ultra low power supply with MOSFETs operating in weak inversion region is proposed. The PTAT voltage generator is a necessary circuit for temperature sensor and bandgap reference circuit under low power supply in minimized CMOS analog integrated circuit. When two MOSFETs operating in weak inversion region are connected between rails, the PTAT voltage generator can be driven even under ultra low power supply voltage. As gate terminals are common in two MOSFETs connected in series and also bulk terminals are common, a gate to bulk voltage for MOS diode in a MOSFET is equal to that in another MOSFET. The proposed PTAT voltage generator operating under supply voltage from 0.2V to 1.8V with -70dB PSRR is fabricated with a standard 0.18μ m n-well CMOS technology and measured to investigate the basic principle. The measured characteristics of output voltage versus temperature fit to the theoretical ones deriving from design principle exactly.

SiO 2 passivation effect on the hydrogen adsorption performance of a Pd/AlGaN-based Schottky diode

In this work, the comprehensive study of the hydrogen adsorption effects on the Pd/AlGaN-based MOS Schottky diode with SiO 2 passivation is demonstrated. Hydrogen sensing performance of the proposed device is significantly enhanced with the insertion of SiO 2 layer. The MOS diode exhibits a maximum sensing response value of 3.3 × 10 5 at 70 °C under a 1% H 2/air gas. Additionally, the operating temperature for the maximum sensing response is decreased from 150 °C to 70 °C with the insertion of SiO 2 layer. Moreover, the lowering of Schottky barrier height is 230 (200) meV for the MOS (MS) diode at room temperature. The hydrogen adsorption effect also largely influence the effective Richardson's constant. Furthermore, the transient-state experiments reveal that the MOS Schottky diode exhibits an activation energy of 14.1 kJ/mol which is lower than the MS Schottky diode (25 kJ/mol). Therefore, hydrogen sensing performance of the AlGaN-based Schottky diode can be significantly enhanced with the SiO 2 passivation on the AlGaN surface.

Electrical characteristics of temperature‐difference liquid phase deposited SiO2 on GaN with (NH4)2Sx treatment

AbstractThe characteristics of a SiO2 film grown on (NH4)2Sx treated GaN by temperature‐difference liquid phase deposition were investigated. Hydrofluorosilicic acid and boric acid were used as deposition solutions. For GaN without the (NH4)2Sx treatment, an Al/SiO2/GaN MOS diode shows poor electrical characteristics due to the native oxides existing at the interface. With (NH4)2Sx treatment of GaN, a stable sulfide‐terminated surface is obtained and the leakage current density of SiO2/GaN is improved from 6.15 × 10–4 A/cm2 to 2.08 × 10–5 A/cm2 at the electric field of 2 MV/cm. The effective oxide charges decrease from 6.09 × 1011 C/cm2 to 2.23 × 1011 C/cm2. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Hydrogen sensing properties of a Pd/SiO 2/AlGaN-based MOS diode

Hydrogen sensing properties of a Pd/AlGaN-based Schottky diode are improved by the deposition of SiO 2 at the metal/semiconductor (MS) interface. The wide Schottky barrier height variation of the MOS diode could be attributed to the large electric field across the SiO 2 layer. This leads to the presence of more hydrogen dipoles caused by the polarization effect. The sensing response of the MOS diode at room temperature (1.3 × 10 5) is comparable to that of the MS one at 150 °C (2.04 × 10 5). Thus, the MOS-type sensing device shows the benefit of low-temperature operation. Kinetic analyses confirm that the short response times of the MOS diode are attributed to high reaction rate at the Pd/SiO 2 interface.

Self-aligned inversion n-channel In 0.2Ga 0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga 2O 3(Gd 2O 3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In 0.2Ga 0.8As on GaAs using TiN as gate metal and Ga 2O 3(Gd 2O 3) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V g = 4 V and V d = 2 V, a low gate leakage of <10 −7 A/cm 2 at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V g = 3 V, V d = 2 V, and an on/off ratio of ∼10 5 in drain current. For comparison, a TiN/Ga 2O 3(Gd 2O 3)/In 0.2Ga 0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10 −8–10 −9 A/cm 2, well-behaved capacitance–voltage ( C– V) characteristics giving a high dielectric constant of ∼16 and a low interfacial density of state of ∼(2∼6) × 10 11 cm −2 eV −1, and an atomically sharp smooth Ga 2O 3(Gd 2O 3)/In 0.2Ga 0.8As interface.

Properties of thick SiO 2/Si structure formed at 120 °C by use of two-step nitric acid oxidation method

Thick (i.e., ∼10 nm) SiO 2/Si structure has been formed at 121 °C by immersion of Si in relatively low concentration HNO 3 followed by that in 68 wt.% HNO 3 (i.e., two-step nitric acid (HNO 3) oxidation method of Si, NAOS) and spectroscopic properties and electrical characteristics of the NAOS SiO 2 layers are investigated. The SiO 2 thickness strongly depends on the concentration of HNO 3 aqueous solutions employed in the initial oxidation, and it becomes the largest at the HNO 3 concentration of 40 wt.%. The MOS diodes with the ∼9 nm SiO 2 layer formed by the NAOS method possess a relatively low leakage current density (e.g., 10 −8 A/cm 2 at the forward bias of 1 V) and it is further decreased by more than one order of magnitude by post-metallization annealing (PMA) in hydrogen at 250 °C. The good leakage characteristic is attributable to atomically flat SiO 2/Si interfaces and high atomic density of 2.30–2.32 × 10 22 atoms/cm 3 of the NAOS SiO 2 layers. High-density interface states are present in as-prepared SiO 2 layers and they are eliminated by PMA in hydrogen.

Mechanism of formation of the response of a hydrogen gas sensor based on a silicon MOS diode

Experimental data on the dependence of the flat-band voltage and relaxation time for the capacitance of the space-charge region in an MOS diode (Pd-SiO2-n-Si) on the hydrogen concentration in a hydrogen/air gaseous mixture are discussed. It is assumed that variation in the flat-band voltage U fb in an MOS structure with the thickness d = 369 nm subjected to a hydrogen/air gaseous mixture can be accounted for by the formation of dipoles in the Pd-SiO2 gap due to polarization of hydrogen atoms (H a ). An analytical expression describing the dependence of variation in the flat-band voltage ΔU fb on the hydrogen concentration \( n_{H_2 } \) was derived. In MOS structures with d ≤ 4 nm (or MOS diodes), the value of ΔU fb is mainly controlled by passivation of the centers responsible for the presence of the surface acceptor-type centers at the SiO2-n-Si interface by hydrogen atoms. Analytical expressions describing the dependences of ΔU fb and the capacitance relaxation time in the space-charge region on \( n_{H_2 } \) are derived. The values of the density of adsorption centers and the adsorption heat for hydrogen atoms at the Pd-SiO2 and SiO2-n-Si interfaces are found.