Abstract The Montgomery modular multiplication finds its application in the area of Cryptography such as RSA algorithm where modular multiplication plays a vital role. The security of the algorithm lies in the number of bits in the multiplier and multiplicand. As the number of bits increase, delay and hardware increases which makes it impractical for the real time application. The objective of this work is to propose an efficient Montgomery algorithm without the use of hardwired multipliers embedded in the Field Programmable Gate Array and reduce the delay. The performance of the multiplier algorithm is highly dependent on the addition module. In order to improve the performance, various architectures for the addition such as carry skip adder, carry look ahead adder, carry save adder, semi and full carry save adder are used. The semi and full carry save addition along with the modification in the Montgomery algorithm helps in improving the speed of the design. The proposed algorithm was compared with the existing algorithm interms of operating frequency and area. The proposed algorithm has been implemented on the stratix FPGA and shows better performance.