Efficient implementation of digit‐serial Montgomery modular multiplier architecture

Abstract

The importance of security in communications has made cryptography one of the most important research for designers. Montgomery modular multiplication is one of the best methods used in cryptosystems. These multipliers can be implemented in different ways including digit-serial architecture. The digit-serial multiplier is an efficient structure for low power and high-speed applications. The architecture of digit-serial multiplier can benefit from the advantage of both serial and parallel structures. This study presents a new digit-serial Montgomery modular multiplier architecture, which takes up less area by reducing internal blocks of the structure. The latency and design complexity of the proposed digit-serial Montgomery multiplier is less than many other similar designs. The critical path delay of the proposed architecture is reduced compared to similar works. The proposed circuit has the flexibility to be used in a large number of bits and can be used for any size of the digit. The simulation results of the proposed multiplier are presented.