A Low Latency Montgomery Modular Exponentiation

Abstract

Abstract RSA (Rivest-Shamir-Adleman) is a widely known and popular public-key cryptosystem used in many security applications. The main mathematical function in RSA is Modular Exponentiation, which is demanding in terms of speed and area. Due to repetitive Modular Multiplications involved in Exponentiation function, it becomes time-consuming, especially for large operands. To accelerate the RSA Encryption/Decryption operation, a reduction in number of Modular Multiplications as well as reduction in clock-cycles to perform one Modular Multiplication operation is required. The main objective of this paper is to develop high-speed, area-efficient hardware Montgomery Modular Exponentiation architecture for RSA Encryption/Decryption operations by using Lookup-Table (LUT) based high-radix Montgomery Modular Multiplier. In this paper, we present a hardware architecture designed to implement Right-to-Left (R-L) Montgomery Modular Exponentiation using a lookup-table based Radix-16 Modular Multiplication with Montgomery reduction. The proposed architecture provides tremendous improvement by reducing the number of clock cycles for one Modular Multiplication from n (operand bit-length) to n/4 cycles. With our implementation results, for Montgomery Modular Exponentiation with Radix-16 lookup-table based Montgomery Multiplier architecture, we are able to achieve computational delay of 6.35ms, 43.16ms, 320.4ms for computing 1024/ 2048/ 4096 bits of Modular Exponentiation, respectively. We were able to achieve significant improvement in terms of time and Time-Area (TA).