Abstract
This paper presents a point multiplication processor over the binary field GF (2233) with internal registers integrated within the point-addition architecture to enhance the Performance Index (PI) of scalar multiplication. The proposed design uses one of two types of finite field multipliers, either the Montgomery multiplier or the interleaved multiplier supported by the additional layer of internal registers. Lopez Dahab coordinates are used for the computation of point multiplication on Koblitz Curve (K-233bit). In contrast, the metric used for comparison of the implementations of the design on different types of FPGA platforms is the Performance Index.
 The first approach attains a performance index of approximately 0.217610202 when its realization is over Virtex-6 (6vlx130tff1156-3). It uses an interleaved multiplier with 3077 register slices, 4064 lookup tables (LUTs), 2837 flip-flops (FFs) at a maximum frequency of 221.6Mhz. This makes it more suitable for high-frequency applications. The second approach, which uses the Montgomery multiplier, produces a PI of approximately 0.2228157 when its implementation is on Virtex-4 (6vlx130tff1156-3). This approach utilizes 3543 slices, 2985 LUTs, 3691 FFs at a maximum frequency of 190.47MHz. Thus, it is found that the implementation of the second approach on Virtex-4 is more suitable for applications with a low frequency of about 86.4Mhz and a total number of slices of about 12305.
Highlights
Elliptic Curve Cryptography (ECC) is a type of asymmetric key (Jwad, Abdulaah, and Effing, 2012) cryptography that provides higher security than Rivest–Shamir–Adleman (RSA) for a smaller key size
This paper aims to enhance the performance index of Point Multiplication (PM) by adding internal registers within the data path of point multiplication, and the proposed designs of PM are implemented on different FPGA platforms
The proposed design of scalar multiplication is based on point addition component
Summary
Elliptic Curve Cryptography (ECC) is a type of asymmetric key (Jwad, Abdulaah, and Effing, 2012) cryptography that provides higher security than Rivest–Shamir–Adleman (RSA) for a smaller key size. A short key is a proper choice for hardware implementations of ECC, especially in devices with restricted resources as they require less area and processing time (Kilts, 2006), Different projective coordinates can be used for point representation, but this work uses the Lopez Dahab coordinate system to skip the inversion process that consumes lots of resources (Bilal and Rajaram, 2010). The efficiency of the highperformance hardware implementation of scalar multiplication depends on the polynomial representation. Both performance metrics, time, and area are desirable to be considered during the design. Hardware implementations require the consideration of speed and area parameters (Strukov, 2006). This work considers two types of binary fields for GF (2233) multipliers: Interleaved and Montgomery
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
