Monolithic 3D Research Articles

Junctionless Poly-GeSn Ferroelectric Thin-Film Transistors with Improved Reliability by Interface Engineering for Neuromorphic Computing

Ferroelectric HfZrOx (Fe-HZO) with a larger remnant polarization (Pr) is achieved by using a poly-GeSn film as a channel material as compared with a poly-Ge film because of the lower thermal expansion that induces higher stress. Then two-stage interface engineering of junctionless poly-GeSn (Sn of ∼5.1%) ferroelectric thin-film transistors (Fe-TFTs) based on HZO was employed to improve the reliability characteristics. With stage I of NH3 plasma treatment on poly-GeSn and subsequent stage II of Ta2O5 interfacial layer growth, the interfacial quality between Fe-HZO and the poly-GeSn channel is greatly improved, which in turn enhances the reliability performance in terms of negligible Pr degradation up to 106 cycles (±2.7 MV/1 ms) and 96% Pr after a 10 year retention at 85 °C. Furthermore, to emulate the synapse plasticity of the human brain for neuromorphic computing, besides manifesting the capability of short-term plasticity, the devices also exhibit long-term plasticity with the characteristics of analog conductance (G) states of 80 levels (>6 bit), small linearity for potentiation and depression of -0.83 and 0.62, high symmetry, and moderate Gmax/Gmin of 9.6. By employing deep neural network, the neuromorphic system with poly-GeSn Fe-TFT synaptic devices achieves 91.4% pattern recognition accuracy. In addition, the learning algorithm of spike-timing-dependent plasticity based on spiking neural network is demonstrated as well. The results are promising for on-chip training, making it possible to implement neuromorphic computing by monolithic 3D ICs based on poly-GeSn Fe-TFTs.

Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs

The recent advancement of wafer bonding and monolithic integration technology offers fine-grained 3-D interconnections to face-to-face (F2F) and monolithic 3-D (M3D) ICs. In this article, we propose a full-chip RTL-to-GDSII physical design solution to build commercial-quality two-tier gate-level F2F and M3D ICs. The state-of-the-art flow named shrunk-2D (S2D) requires shrinking of standard cells and interconnects by a factor of 50% to fit into the target 3-D footprint of a two-tier design. This, unfortunately, necessitates commercial place/route engines that handle one node smaller geometries, which can be challenging and costly. Our flow named compact-2D (C2D) does not require any geometry shrinking. Instead, C2D implements a 2-D IC with scaled interconnect $RC$ parasitics and contracts the layout to the 3-D integrated circuit footprint. In addition, C2D offers post-tier-partitioning optimization (post-TP opt) which is completely missing in S2D. This additional optimization step is shown to be effective in fixing timing violations caused by intertier 3-D routing overhead. Lastly, we present a methodology to reuse the routing result of post-TP opt for the final GDSII generation. Our experimental results show that at iso-performance, C2D offers up to 28.0% power reduction and 15.6% silicon area savings over commercial 2-D ICs without any routing resource overhead.

Vacuum‐Dried 3D Holey Graphene Frameworks Enabling High Mass Loading and Fast Charge Transfer for Advanced Batteries

Monolithic 3D graphene frameworks (GFs) electrode materials have exhibited the great potential for energy storage devices. However, most approaches for fabricating 3D GF require expensive and sophisticated drying techniques, and the current achieved 3D GF electrodes usually hold a relatively low mass loadings of the active materials with low areal capacity, which is not satisfactory for practical application. Herein, a convenient, economic, and scalable drying approach is developed to fabricate 3D holey GFs (HGFs) by a vacuum‐induced drying (VID) process for the first time. This binder‐free 3D HGF electrode with high mass loading can obtain extraordinary electrochemical performance for lithium‐ion batteries (LIBs) due to the 3D holey graphene network owning a highly interconnected hierarchical porous structure for fast charge and ion transport. The HGF electrode with high mass loading of 4 mg cm−2 exhibits superior rate performance and delivers an areal capacity as high as 5 mAh cm−2 under the current density of 8 mA cm−2 even after 2000 cycles, considerably outperforming those of state‐of‐the‐art commercial anodes and some representative anodes in other studies. This facile drying approach and robust realization of high areal capacity represent a critical step for 3D graphene‐based electrode materials toward practical electrochemical energy storage devices.

Epitaxial Lift-Off Technology for Large Size III–V-on-Insulator Substrate

III-V materials can be a very good channel candidate for monolithic 3D (M3D) integration due to the potential of high-performance and lower process temperature as compared with Si, since a low process temperature is crucial to avoid degradation of bottom devices. For III-V M3D integration, material transfer techniques are important, and such processes should be enabled by low process costs on a large wafer scale. In this study, we propose an InGaAs channel transfer technique by wafer bonding, epitaxial lift-off and III-V layers grown on Si substrate. Effective mobility of fabricated MOS HEMTs using transferred InGaAs layer was 1.3 times higher than that of Si MOSFETs. The proposing channel transfer technique would be useful for M3D integration because it provides wafer scalability, cost-effectiveness, back-gate biasing, and etc.

A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits

Monolithic 3-D (M3D) integration has the potential to achieve significantly higher device density compared to 3-D integration based on through-silicon vias. We propose a test solution for M3D ICs based on dedicated test layers, which are inserted between functional layers. We evaluate the cost associated with the proposed design-for-test (DfT) solution and compare it with that for a potential DfT solution based on the IEEE Std. P1838. Our results show that the proposed DfT solution is more cost-efficient than the P1838-based DfT solution for a wide range of interlayer via density. We also present a test scheduling and optimization technique for wafer-level testing of M3D ICs. The proposed technique provides test schedules with minimum test time under power consumption and probe pad constraints.

Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory.

In order to simulate a circuit by applying various logic circuits and full chip using the HSPICE model, which can consider electrical coupling proposed in the previous research, it is investigated whether additional electrical coupling other than electrical coupling by top and bottom layer exists. Additional electrical coupling were verified through device simulation and confirmed to be blocked by heavily doped source/drain. Comparing the HSPICE circuit simulation results using the newly proposed monolithic 3D NAND (M3DNAND) structure in the technology computer-aided design (TCAD) mixed-mode and monolithic 3D inverter (M3DINV) unit cell model was once more verified. It is possible to simulate various logic circuits using the previously proposed M3DINV unit cell model. We simulated the operation and performances of M3DNAND, M3DNOR, 2 × 1 multiplexer (MUX), D flip-flop (D-FF), and static random access memry (SRAM).

Highly Efficient UV–Visible Photocatalyst from Monolithic 3D Titania/Graphene Quantum Dot Heterostructure Linked by Aminosilane

AbstractAs rapidly growing environmental pollution demands the development of efficient photocatalytic materials, tremendous attention has been drawn to TiO2, a widely used photocatalytic material with cost‐effectiveness, stability, and outstanding reactivity. To maximize its photocatalytic efficiency by enhancing the photogenerated charge separation, lowering the intrinsically large bandgap (3.2 eV) of TiO2 is a key problem to be overcome. Herein, a new design is reported for an efficient photocatalyst realized by heterostructuring a 3D nanostructured TiO2 monolith (3D TiO2) and graphene quantum dots (GQDs) through using 3‐aminopropyltriethoxysilane (APTES) as a linker. The incorporation of APTES between the TiO2/GQD interface enables the formation of a charge injection‐type heterostructure, as confirmed by transient absorption spectroscopy, providing improvement of both visible absorption and charge separation. As a result, the heterostructure exhibits a 242% enhanced photocatalytic performance compared to that of nonheterostructured 3D TiO2 under visible irradiation, demonstrating its promising potential for practical photocatalytic applications in environmental remediation.

An Interlayer Interconnect BIST and Diagnosis Solution for Monolithic 3-D ICs

Monolithic 3-D (M3D) integration offers higher-density integration compared to 3-D integration based on through-silicon vias. Advances in testing are however needed to screen defects in M3D integration without significantly impacting manufacturing cost. We propose a built-in-self-test (BIST) solution to target shorts and opens in interlayer vias (ILVs). In the proposed solution, scan cells at the interface of two layers are stitched into a twisted-ring counter (TRC) using their functional outputs and ILVs. The interface-register cells launch and capture tests, and a test path consists of ILVs and a multiplexer. We map the problem of minimizing the length of the wires added to stitch the TRC to that of finding a minimum-cost Hamiltonian circuit in a weighted bipartite graph. Since the weighted Hamiltonian circuit problem is NP-Complete, we propose a heuristic algorithm for this problem. We also propose a framework based on artificial neural network to carry out diagnosis when a chip fails the proposed test. We show using simulations that the proposed BIST solution can detect all opens and shorts. We also show using simulations that the proposed diagnosis framework can accurately estimate the size of defects in ILVs.

ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support

We present a novel 3D-SRAM cells using a monolithic 3D integration technology for realizing both robustness of the cell and in-memory Boolean logic computing capability. The proposed two-layer cell designs make use of additional transistors over the SRAM layer to enable assist techniques as well as provide logic functions (such as AND/NAND, OR/NOR, and XNOR/XOR) or enable content addressability without degrading cell density. Through analysis, we provide insights into the benefits provided by three memory assist and two logic modes, and we evaluate the energy efficiency of our proposed design. We show that the assist techniques improve SRAM read stability by $2.2\times $ and increase the write margin by 17.6% while staying within the SRAM footprint. By the virtue of increased robustness, the cell enables seamless operation at lower supply voltages; and thereby, ensures energy efficiency. Energy delay product reduces by $1.6\times $ over standard 6T SRAM with a faster data access. When computing bulk In-memory operations, $6.5\times $ energy saving is achieved as compared to computing outside the memory system.

Metal-Organic Frameworks/Conducting Polymer Hydrogel Integrated Three-Dimensional Free-Standing Monoliths as Ultrahigh Loading Li-S Battery Electrodes.

The lithium-sulfur (Li-S) system is a promising material for the next-generation of high energy density batteries with application extending from electrical vehicles to portable devices and aeronautics. Despite progress, the energy density of current Li-S technologies is still below that of conventional intercalation-type cathode materials due to limited stability and utilization efficiency at high sulfur loading. Here, we present a conducting polymer hydrogel integrated highly performing free-standing three-dimensional (3D) monolithic electrode architecture for Li-S batteries with superior electrochemical stability and energy density. The electrode layout consists of a highly conductive three-dimensional network of N,P codoped carbon with well-dispersed metal-organic framework nanodomains of ZIF-67 and HKUST-1. The hierarchical monolithic 3D carbon networks provide an excellent environment for charge and electrolyte transport as well as mechanical and chemical stability. The electrically integrated MOF nanodomains significantly enhance the sulfur loading and retention capabilities by inhibiting the release of lithium polysulfide specificities as well as improving the charge transfer efficiency at the electrolyte interface. Our optimal 3D carbon-HKUST-1 electrode architecture achieves a very high areal capacity of >16 mAh cm-2 and volumetric capacity (CV) of 1230.8 mAh cm-3 with capacity retention of 82% at 0.2C for over 300 cycles, providing an attractive candidate material for future high-energy density Li-S batteries.

Monolithic 3D printing of embeddable and highly stretchable strain sensors using conductive ionogels

Medical training simulations that utilize 3D-printed, patient-specific tissue models improve practitioner and patient understanding of individualized procedures and capacitate pre-operative, patient-specific rehearsals. The impact of these novel constructs in medical training and pre-procedure rehearsals has been limited, however, by the lack of effectively embedded sensors that detect the location, direction, and amplitude of strains applied by the practitioner on the simulated structures. The monolithic fabrication of strain sensors embedded into lifelike tissue models with customizable orientation and placement could address this limitation. The demonstration of 3D printing of an ionogel as a stretchable, piezoresistive strain sensor embedded in an elastomer is presented as a proof-of-concept of this integrated fabrication for the first time. The significant hysteresis and drift inherent to solid-phase piezoresistive composites and the dimensional instability of low-hysteresis piezoresistive liquids inspired the adoption of a 3D-printable piezoresistive ionogel composed of reduced graphene oxide and an ionic liquid. The shear-thinning rheology of the ionogel obviates the need to fabricate additional structures that define or contain the geometry of the sensing channel. Sensors are printed on and subsequently encapsulated in polydimethylsiloxane (PDMS), a thermoset elastomer commonly used for analog tissue models, to demonstrate seamless fabrication. Strain sensors demonstrate geometry- and strain-dependent gauge factors of 0.54–2.41, a high dynamic strain range of 350% that surpasses the failure strain of most dermal and viscus tissue, low hysteresis (<3.5% degree of hysteresis up to 300% strain) and baseline drift, a single-value response, and excellent fatigue stability (5000 stretching cycles). In addition, we fabricate sensors with stencil-printed silver/PDMS electrodes in place of wires to highlight the potential of seamless integration with printed electrodes. The compositional tunability of ionic liquid/graphene-based composites and the shear-thinning rheology of this class of conductive gels endows an expansive combination of customized sensor geometry and performance that can be tailored to patient-specific, high-fidelity, monolithically fabricated tissue models.

A high sensitivity 4π view gamma imager with a monolithic 3D position-sensitive detector

Abstract Imaging is an effective way to survey gamma radiation hotspots in nuclear safety, public health and homeland security applications. The existing gamma imagers either equip a collimator , which limits the imaging field of view (FOV) and sensitivity, or work without a collimator but require a high performance detector with sophisticated data processing and image reconstruction methods, e.g. the Compton camera. In this work, we demonstrate the feasibility of a high sensitivity 4 π view gamma imager design concept. Based on the photon event density distribution inside a monolithic 3D position-sensitive detector, the imager reconstructs the 4 π view of the surrounding gamma hotspots that the detector is exposed to. Monte Carlo simulations and experiments were conducted for several configurations of surrounding sparse gamma point sources in the energy range from 0.1 to 1.5 MeV. The results show that the reconstructed 4 π view image can identify multiple gamma hotspots, with the hotspots’ positioning accuracy and resolution dependent on the detector’s intrinsic resolution and the statistics of the acquired data. We conclude that the proposed design can be used for surveying gamma hotspots in nuclear security applications.

(Invited) Nano Carbon and Polymeric Materials for Energy Conversion and Storage

Green energy technologies have been highly demanded for a sustainable development. In this talk, our recent studies for the electricity conversion/storage using nano carbon and polymeric materials will be presented. These will include the material design, synthesis, and device fabrication, targeting for high energy efficiency and understanding the mechanism using simpler or cheap materials. Recent five references: "Polymeric Graphene Bulk Materials with a 3D Cross-Linked Monolithic Graphene Network", Wangqiao Chen, Peishuang Xiao, Honghui Chen, Hongtao Zhang, Qichun Zhang, and Yongsheng Chen*, Mater ., 2018, 1802403."Nonfullerene Tandem Organic Solar Cells with High Performance of 14.11%", Lingxian Meng, Yamin Zhang, Xiangjian Wan*, Chenxi Li, Xin Zhang, Yanbo Wang, Xin Ke, Zuo Xiao, Liming Ding*, Ruoxi Xia, Hin-Lap Yip, Yong Cao, Yongsheng Chen*, Science , 2018, 361, 1094-1098."Monolithic 3D Cross-linked Polymeric Graphene Materials and the Likes: Preparation and Their Redox Catalytic Applications",Yanhong Lu, Yanfeng Ma, Tengfei Zhang, Yang Yang, Lei Wei, and Yongsheng Chen , Am. Chem. Soc., 2018, 140 (37), pp 11538–11550."Ultra-Broadband Wide-Angle Terahertz Absorption Properties of 3D Graphene Foam",Zhiyu Huang, Honghui Chen, Yi Huang,* Zhen Ge, Ying Zhou, Yang Yang, Peishuang Xiao, Jiajie Liang, Tengfei Zhang, Qian Shi, Guanghao Li, and Yongsheng Chen, Funct. Mater. , 2017, 1704363“Macroscale light propulsion of 3D cross-linked graphene ”, Tengfei Zhang†, Huicong Chang†, Yingpeng Wu†, Peishuang Xiao, Ningbo Yi, Yanhong Lu, Yanfeng Ma, Yi Huang, Kai Zhao, Xiaoqing Yan, Zhibo Liu, Jianguo Tian and Yongsheng Chen*, Nature Photon., 2015, 9, 471-476

System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs

As 2-D scaling reaches its limit, monolithic 3-D (M3D) IC is a leading contender for continuing equivalent scaling. Although M3D shows power and performance benefits over 2-D designs, designing a power delivery network (PDN) for M3D is challenging. In this paper, for the first time, we present a system-level PDN model of M3D designs focusing on both resistive (IR) and inductive ( $\text{L}di/dt$ ) components of power supply integrity. In addition, we present frequency- and time-domain analyses of M3D PDNs. We show that the additional resistance in M3D PDNs, while being worse for resistive drops, improves resiliency against ac current noise showing 35.9% peak impedance reduction compared to 2-D PDNs during worst case resonant oscillations. Then, we present methodologies to improve power supply integrity of M3D designs based on the observations. Our optimization methodologies offer up to 32.6% and 17.0% static and dynamic voltage drop reduction compared to the baseline M3D designs, respectively, showing 9.0% lower dynamic voltage drop compared to the 2-D counterparts.

Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs

Monolithic inter-layer vias (MIVs) used in 3D integration technology are much smaller than through-silicon vias (TSVs) used in TSV-based 3D integration. Thus, monolithic 3D integration provides shorter wire length, better performance, and lower power consumption than TSV-based 3D integration. Multi-tier monolithic 3D integration stacks more than two silicon layers, thereby increasing the device density, which reduces the wire length and power consumption and improves performance further than two-tier monolithic 3D integration. Since the size of an MIV is comparable to that of a local via, the wire lengths of multi-tier gate-level monolithic 3D IC layouts are expected to be close to the ideal wire length reduction ratio, for example, 29, 42, and 50 percent for two-, three-, and four-tier designs, respectively. However, it is still unknown whether it would be possible to achieve the ideal wire length reduction ratios by multi-tier gate-level monolithic 3D integration. In this paper, we propose an efficient routing methodology to design multi-tier monolithic 3D ICs. Using the design methodology, we design two- to eight-tier gate-level monolithic 3D IC layouts and thoroughly investigate the wire length characteristics of the layouts. The simulation results show that the proposed routing methodology reduces the wire length by 12 to 53 percent compared to the 2D designs. In addition, the proposed routing methodology builds multi-tier monolithic 3D IC layouts more efficiently than a state-of-the-art methodology with comparable routed wire length.

Slingshot Pull-In Operation for Low-Voltage Nanoelectromechanical Memory Switches

A novel “slingshot” pull-in operation is proposed to lower the operation voltage ( ${V}_{\text {DD}}$ ) of nanoelectromechanical (NEM) memory switches for the implementation of monolithic 3-D (M3D) CMOS-NEM hybrid reconfigurable logic (RL) circuits. According to the theoretical calculation and experimental data, the proposed “slingshot” pull-in operation lowers ${V}_{\text {DD}}$ of the NEM memory switches by ~0.84 times. It contributes to the overall ${V}_{\text {DD}}$ reduction and chip density boost of M3D CMOS-NEM RL circuits.

3D-printed highly porous and reusable chitosan monoliths for Cu(II) removal

Removal of heavy metal pollution has received considerable research attention due to its severe effects on human health. In the present study, for the first time, a reusable monolithic 3D porous adsorbing filter was fabricated by integrating 3D printing technique with a natural adsorbent (chitosan), which is a low-cost and highly effective solution for heavy metal removal. The –NH2 and –OH functional groups found on the highly porous monoliths were capable of adsorbing metal ions. Further analyses revealed that the adsorption capacity increases with the filter’s surface area, with T = 25 °C and pH 5.5 representing the optimal working conditions. The maximum adsorption capacity of 13.7 mg/g (calculated by using the total mass) was measured for the filter with skewed hexagonal holes. The pseudo-first-order equation and Langmuir isotherm model presented a good fit to the experimental data, thus accurately describing the adsorption kinetics and the adsorption equilibrium. The monolithic chitosan-loaded filter exhibited a superior adsorption kinetics of 2.2 mg/(g min) for Cu(II) removal. Findings yielded by the desorption experiment also demonstrated that EDTA can desorb the metal ions from the monoliths, and its ~ 92% desorption capacity indicates high reusability. All results reported in this work indicate that 3D printing offers an alternative, cost-effective and facile approach for fabricating structured adsorbents with tunable structural and chemical properties for use in metal ion removal.

Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines

Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect of M3D integration on their inductance densities and quality factors has been analyzed. The impact of shields on M3D inductors has been investigated, as well as the shunting of multiple metal layers to form multimetal inductors. In an attempt to improve the area efficiency of M3D RF/AMS circuits, the potential of placing bottom-tier blocks underneath top-tier inductors has been identified, and a set of guidelines has been proposed to maximize the inter-tier electromagnetic isolation. These guidelines deal with the suitable position of both low- and high-frequency blocks, their wiring, as well as the type of shield that is needed between them and the inductors. To prove the efficiency of these guidelines, an array of bottom-tier resistors has been placed underneath a top-tier inductor, resulting in more than 50 dB of inter-tier isolation for frequencies up to 20 GHz.

X3D: Heterogeneous Monolithic 3D Integration of “X” (Arbitrary) Nanowires: Silicon, III–V, and Carbon Nanotubes

We experimentally demonstrate a new paradigm for monolithic three-dimensional (3D) integration: X3D, which enables a wide range of semiconductors - including silicon (Si), III-V, and nanotechnologies such as carbon nanotubes (CNTs) - to be heterogeneously integrated together in monolithic 3D integrated systems. Such flexible heterogeneous integration has potential for a wide range of applications, as each layer of monolithic X3D integrated circuits (ICs) can be customized for specific functionality (e.g., wide-bandgap III-V-based circuits for power management, CNT field-effect transistors (CNFETs) for energy-efficient computing, and tailored materials for custom sensors or imagers). As a case study, we experimentally demonstrate monolithic X3D ICs with five vertical circuit layers heterogeneously integrating three different semiconductors: Si junctionless nanowire field-effect transistors (JNFETs), III-V JNFETs, and CNFETs (also junctionless). The layers of monolithic X3D IC are, from bottom-to-top: Si p-JNFETs, n-CNFETs, Si n-JNFETs, p-CNFETs, and III-V n-JNFETs. Each layer is fabricated using an identical process flow for ease of integration. Importantly, we show that circuits fabricated on each vertical layer are agnostic to subsequent monolithic X3D processing, experimentally demonstrating ability to interleave these “X” (arbitrary) semiconductors in arbitrary vertical ordering. As a final demonstration, we fabricate complementary digital logic circuits comprising different technologies that span multiple vertical circuit layers. This work demonstrates a new paradigm for ICs, allowing for flexible and customizable electronic systems.

Freestanding 3D nanoporous Cu@1D Cu2O nanowire heterostructures: from a facile one-step protocol to robust application in Li storage

Herein, a one-step UPO-assisted dealloying protocol was developed to synthesize monolithic 3D NPC@1D Cu2O NWN heterostructures with superior Li storage properties.