Monolithic 3D Research Articles

Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture

Monolithic 3D (M3D) integration has been emerged as a promising technology for fine-grained 3D stacking. As the M3D integration offers extremely small dimension of via in a nanometer-scale, it is beneficial for small microarchitectural blocks such as caches, register files, translation look-aside buffers (TLBs), etc. However, since the M3D integration requires low-temperature process for stacked layers, it causes lower performance for stacked transistors compared to the conventional 2D process. In contrast, non-volatile memory (NVM) such as magnetic RAM (MRAM) is originally fabricated at a low temperature, which enables the M3D integration without performance degradation. In this paper, we propose an energy-efficient unified L2 TLB-cache architecture exploiting M3D-based SRAM/MRAM hybrid memory. Since the M3D-based SRAM/MRAM hybrid memory consumes much smaller energy than the conventional 2D SRAM-only memory and 2D SRAM/MRAM hybrid memory, while providing comparable performance, our proposed architecture improves energy efficiency significantly. Especially, as our proposed architecture changes the memory partitioning of the unified L2 TLB-cache depending on the L2 cache miss rate, it maximizes the energy efficiency for parallel workloads suffering extremely high L2 cache miss rate. According to our analysis using PARSEC benchmark applications, our proposed architecture reduces the energy consumption of L2 TLB + L2 cache by up to 97.7% (53.6% on average), compared to the baseline with the 2D SRAM-only memory, with negligible impact on performance. Furthermore, our proposed technique reduces the memory access energy consumption by up to 32.8% (10.9% on average), by reducing memory accesses due to TLB misses.

A Multiply-and-Accumulate Array for Machine Learning Applications Based on a 3D Nanofabric Flow

To keep pushing Moores law cadence and improve integrated circuits area, delay, and power, novel fabrication schemes such as parallel and monolithic 3D integration have been recently proposed. While parallel 3D does not enable very fine-grained vertical connections, monolithic 3D currently only offers a limited number of transistor tiers due to the high cost of the additional masks and processing steps. In our previous work, we introduced a novel 3D integration scheme called 3D Nanofabric. Inspired by the 3D NAND flash process, the flow consists of N identical vertical tiers where multiple vertical layers can be patterned at once, reducing the manufacturing cost significantly. In this paper, we propose to use our 3D Nanofabric flow to design low-footprint Multiply-And-Accumulate units (MAC). As a MAC unit can be designed using a regular array organization, we show how it can be spread across multiple vertical layers using the 3D Nanofabric flow, while respecting the different layout constraints. Through circuit-level evaluations, we show that for a 64-input bit multiplier, the area and area-delay-product are decreased by 21.0x and 16.7x, respectively, compared to a traditional 2D implementation using a 28nm FDSOI technology, with only a 43% energy overhead. Additionally, we show how to build a systolic 3D MAC array aimed at convolutional neural networks. Through architectural evaluations, we demonstrate that when running VGG-16, our 3D MAC array can improve the TOPs/mm2 by 2.8x compared to a TPU-like 2D systolic array.

Insights into light and mass transport in nanoparticle-based aerogels: the advantages of monolithic 3D photocatalysts

The interest of nanoparticle-based aerogels—3-dimensional (3D) nanoparticle assemblies of macroscopic sizes—in photocatalysis is mainly their versatility for tailoring properties.

Design of monolithic closed-cell polymer foams via controlled gas-foaming for high-performance solar-driven interfacial evaporation

A monolithic 3D interfacial steam generator is successfully constructed via a controlled gas-foaming technique and demonstrated for high-performance solar evaporation and desalination under a variety of realistic conditions.

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

Electrical Coupling of Monolithic 3D Inverters (M3INVs): MOSFET and Junctionless FET

In this paper, we investigated the electrical coupling between the top and bottom transistors in a monolithic 3-dimensional (3D) inverter (M3INV) stacked vertically with junctionless field-effect transistor (JLFET), which is one of candidates to replace metal-oxide-semiconductor field-effect transistors (MOSFET). Currents, transconductances, and gate capacitances of the top N-type transistor at the different gate voltages of the bottom P-type transistor as a function of thickness of inter-layer dielectric (TILD) and gate channel length (Lg) are simulated using technology computer-aided-design (TCAD). In M3INV stacked vertically with MOSFET (M3INV-MOS) and JLFET (M3INV-JL), the variations of threshold voltage, transconductance, and capacitance increase as TILD decreases and they increase as Lg increases, and thus there is a strong coupling in M3INV at the range of TILD ≤ 30 nm. In M3INV, the coupling between stacked JLFETs in M3INV-JL is larger than that between MOSFETs in M3INV-MOS at the same TILD and Lg. The switching threshold voltage (Vm) and noise margins (NMs) of M3INV are calculated from the voltage transfer characteristics (VTC) simulated with TCAD mixed-mode. As the gate lengths of M3INV-MOS and M3INV-JL increase, the Vm variations increase and decrease, respectively. The smaller the gate lengths of M3INV-NOS and M3INV-JL, the larger and smaller the variation of Vm, respectively. The noise margin of M3INV-MOS is larger and better for inverter characteristics than one of M3INV-JL. M3INV-MOS has less electrical coupling than M3INV-JL.

Why In2O3 Can Make 0.7 nm Atomic Layer Thin Transistors.

In this work, we demonstrate enhancement-mode field-effect transistors by an atomic-layer-deposited (ALD) amorphous In2O3 channel with thickness down to 0.7 nm. Thickness is found to be critical on the materials and electron transport of In2O3. Controllable thickness of In2O3 at atomic scale enables the design of sufficient 2D carrier density in the In2O3 channel integrated with the conventional dielectric. The threshold voltage and channel carrier density are found to be considerably tuned by channel thickness. Such a phenomenon is understood by the trap neutral level (TNL) model, where the Fermi-level tends to align deeply inside the conduction band of In2O3 and can be modulated to the bandgap in atomic layer thin In2O3 due to the quantum confinement effect, which is confirmed by density function theory (DFT) calculation. The demonstration of enhancement-mode amorphous In2O3 transistors suggests In2O3 is a competitive channel material for back-end-of-line (BEOL) compatible transistors and monolithic 3D integration applications.

(Invited) Epitaxial Growth of Ge/III-V Films and Hetero-Layer Lift-off for Ultra-Thin GeOI Fabrication

Monolithic 3D (M3D) integration has been thought of as an attractive idea to realize multi-functional heterogeneous integration devices. M3D integration enables us to combine logic devices with different functional devices such as memory, sensor, or optics to create extremely compact and efficient system-on-chips. Ge and III-V compound semiconductors are expected to be implemented as high mobility channel materials and optical components which cannot be realized with Si. The layer transfer technique with low processing temperature has great potential for stacking non-lattice-matched crystalline materials for M3D ICs. Here, we discuss the layer transfer technology utilizing high quality epitaxial growth, low-temperature direct bonding and advanced epitaxial lift-off (ELO) process, which reveals the applicability of transferred layers for heterogeneous integration.The low temperature ELO process is essential for realizing reliable layer transfer with different materials because the process is almost free from the issues of thermal expansion mismatch. Process flow of GaAs or Ge layer transfer with ELO process is described in Fig. 1. First of all, a lattice-matched single crystal GaAs or Ge layer is epitaxially grown on GaAs substrate with an AlAs release layer by MOCVD. Subsequently, Al2O3 layer is deposited on the epitaxial layer by atomic layer deposition (ALD). ALD Al2O3 layer serves as the buried oxide (BOX) and the passivation layer for Ge or GaAs surface. Then, Ge or GaAs layer is patterned using photolithography. The patterned GaAs or Ge/AlAs/GaAs donor wafer is then bonded on host substrate by direct bonding technique with wet activation process. Finally, the epitaxial GaAs or Ge layer is transferred on host substrates by splitting GaAs donor wafer from AlAs layer with HCl side etching thanks to extremely high etching selectivity. Note that the fabrication of patterned transfer layer is effective in shortening the required time of ELO process. In this ELO process, the thickness of a transferred layer can be control by epitaxial layer thickness. After the layer transfer process, the released donor GaAs wafer can be reclaimed and reused for the subsequent re-epitaxial growth to reduce the process cost.Figs. 2 (a) and (b) show cross-sectional SEM and TEM images of fabricated GeOI substrate with different BOX structures. Ge pattern edge shows no peeling from SiO2(100nm)/Si substrate, indicating strong bonding strength at the pattern edge. In Fig. 2 (b), the bonding interface is clearly observed at Al2O3(5nm)/SiO2(50nm) interface formed by the wet activation process. The bonding interface exhibits very smooth and no defect. There is no observable defect in transferred Ge layer, suggesting dislocation density is below TEM detection limit. Compared to Smart-CutTM technique, ELO process has significant advantages in terms of crystal quality, thickness control and the surface flatness thanks to totally low temperature processing.To reduce wafer-scale thickness variation, etching stopper (ES) technique with high etching selectivity is quite useful. As a donor wafer, we prepare Ge active layer (20nm)/SiGe ES layer (5nm)/Ge buffer layer/AlAs/GaAs structures. Here, the SiGe layer serves as ES against the etching of Ge buffer layer to control the final GeOI thickness and attain the wafer-scale thickness uniformity. In addition, Si passivation on Ge surface was performed during initial epitaxial growth of donor wafer since Si passivation was proved to be effective in reducing interfacial trap density (D it) between Ge and oxide. After ELO process, Ge buffer layer /SiGe ES layer/Ge active layer / Al2O3 /SiO2/Si heterostructure was obtained. Then, the top Ge buffer layer was removed in HCl/H2O2 solution. We found the etching selectivity was more than 30 between Ge and SiGe layer, which is high enough to yield very smooth SiGe surface. Finally, SiGe layer was removed by TMAH preferentially.Further conformal thinning of Ge active layer was performed by the cyclic dry oxidation/wet digital etching (DE) at room temperature. In addition to thickness control with the etching rate of about 0.8 nm/cycle, it is found that dozens digital etching (DDE) process is effective for reducing Ge surface roughness. Finally, UTB GeOI substrates with high crystal quality down to 3 nm have been successfully fabricated through SiGe ES and DDE processes. Ultra-smooth GeOI surface with reduced thickness fluctuation was confirmed after DDE by TEM cross-sectional images, resulting in significant improvement of device performances. Figure 1

(Invited) Three-Dimensional Nanostructuring of Metal-Organic Frameworks for Energy Applications

Metal-organic frameworks (MOFs) are a growing family of microporous materials that are attracting significant research and industrial interest, thanks to their unique features including a tuneable and narrow intrinsic pore size distribution, and very high surface area. MOFs are also being increasingly used as a precursor for the preparation of well-dispersed metal-containing carbon electrodes. A major challenge remains the three-dimensional structuring of MOFs into hierarchical functional morphologies and their integration as active elements in electrical material systems, due to their usually low electronic conductivities. Here, we present some flexible strategies for the structuring of MOFs into three-dimensional morphologies and their application for energy storage. In particular, we focus on lithium–sulfur (Li–S) batteries as a promising system for the next-generation of high energy density batteries. Despite progress, the energy density of current Li–S technologies is still below that of conventional intercalation-type cathode materials, due to limited stability and utilization efficiency at high sulfur loading.We demonstrate a highly performing free-standing monolithic electrode architecture for Li–S batteries with superior electrochemical stability and energy density [1]. The electrode layout consists of a highly conductive three-dimensional network of N,P co-doped carbon with well-dispersed metal-organic frameworks nano-domains of ZIF-67 and HKUST-1. The hierarchical monolithic 3D carbon networks provides an excellent environment for charge and electrolyte transport as well as mechanical and chemical stability. The electrically-integrated MOF nano-domains significantly enhance the sulfur loading and retention capabilities by inhibiting the release of lithium polysulfide specifies as well as improving the charge transfer efficiency at the electrolyte interface. Our optimal 3D carbon-HKUST-1 electrode architecture achieves a very high areal capacity of > 16 mAh cm−2 with a capacity retention of 82 % at 0.2C for over 300 cycles, providing an attractive candidate material for future high energy density Li–S batteries. We believe that our approaches provide some promising directions for the engineering of functional MOF morphologies for electrochemistry. References Liu, B.; Bo, R.; Taheri, M.; Di Bernardo, I.; Motta, N.; Chen, H.; Tsuzuki, T.; Yu, G.; Tricoli, A. Nano Lett. 2019, 19, (7), 4391-4399.

Low Thermal Budget (<250 °C) Dual-Gate Amorphous Indium Tungsten Oxide (IWO) Thin-Film Transistor for Monolithic 3-D Integration

We experimentally demonstrate back-end-of-the-line (BEOL) compatible ( ${I}_{D{,SAT}}$ of $370~\mu \text{A}/\mu \text{m}$ , and on–off ratio $> 4\times 10^{9}$ at ${V}_{DS} = 1$ V and ${V}_{GS}$ – ${V}_{TH}= 2$ V. We identify fundamental transport mechanisms that limit electron mobility in amorphous IWO transistors at different gate-bias ( ${V}_{GS}$ ) and temperature. Benchmarking reveals that amorphous IWO FETs are promising candidate for in situ transistor fabrication in the BEOL for enabling high-performance monolithic 3-D (M3-D) integrated circuits.

Programmable Building Blocks via Internal Stress Engineering for 3D Collective Assembly

AbstractThe collective assembly of finite building blocks can induce complicated scaled‐up architecture for structural diversity and multifunctionality. In this study, the concept of 2D to 3D shape morphing via frontal photopolymerization is employed for the rapid and repetitive fabrication of geometrically tailorable building blocks. The photoabsorber generates an internal stress gradient which induces a mismatch of volumetric shrinkage within a photocured monolithic 3D structure. The final 3D curvilinear architecture is investigated through systematic analysis by controlling the spatiotemporal conditions of 3D shape morphing. The spatiotemporal effect consists of pre/postcuring methods and geometry of the 2D patterns inspired by fractal elements including even/odd condition, spirality, and self‐similarity. Finally, the concept of collective assembly is introduced to construct multiple objective architectures. Each morphed structure contributes to the assembly of hierarchical 3D structures as a building block. Inspired by famous architectures, the collective hierarchical 3D structures are demonstrated by replicating the form of certain landmarks. In addition, scaled‐up assembled 3D structure can withstand 150 times of its own weight and can be applied for the frame of electronic devices. The collective assembly of programmable building blocks has the potential for various versatile applications in rapid prototypes of optical metamaterials, antennas, and curved electronic devices.

Single event upset for monolithic 3-D integrated 6T SRAM based on a 22 nm FD-SOI technology: Effects of channel size and temperature

The single event upset (SEU) for monolithic 3-D (M3D) 6T SRAM with different channel sizes was investigated based on a 22 nm fully-depleted silicon-on-insulator (FD-SOI) technology over a temperature range from 210 K to 390 K. Compared with planar SRAM, M3D SRAM exhibits higher SEU sensitivity and increasing the transistor size does not work in mitigating the SEU in M3D. It is also demonstrated that the SEU sensitivity of M3D 6T SRAM enhances with temperature rising after the incident of 127I while it decreases after the striking of 209Bi. The reason can primarily be explained by the different influence ranges of striking heavy ions, which affect the ionized charge transport.

Monolithic 3D stacked multiply-accumulate units

The monolithic 3D stacking (M3D) reduces the critical path delay, leveraging 1) short latency of a monolithic inter-tier via (MIV) and 2) short 2D interconnect and cell delay through smaller footprint. In this paper, we propose M3D stacked multiply-accumulate (MAC) units; MAC units have a relatively large number of long wires. With the Samsung 28 nm ASIC library, the M3D stacked MAC units reduce the critical path delay by up to 28.9%, compared to the conventional 2D structure. In addition, the M3D stacked MAC units reduce dynamic energy and leakage power by up to 9.6% and 21.7%, respectively. Compared to the TSV stacked MAC units, the M3D stacked MAC units consume less dynamic energy and leakage power by up to 37.1% and 73.6%, respectively. Though the 3D stacking technology inevitably causes higher peak temperature than the 2D structure, our thermal results show that the peak temperature of the M3D stacking is always lower than that of the TSV-based 3D stacking. Furthermore, when the size of the MAC unit is optimized in convolutional neural network (CNN) applications, the peak temperature of the M3D stacking is 88.3 °C at most, which is still under the threshold temperature.

Energy-Efficient Monolithic 3-D SRAM Cell With BEOL MoS2 FETs for SoC Scaling

In this article, we propose an energy-efficient monolithic 3-D (M3D) three-tier SRAM cell with back-end-of-the-line (BEOL) back-gated (BG) MoS2 FETs. The impacts of wire routing resistance and capacitance, gate topology of MoS2 FETs, and the layout optimization of multitier 6T SRAM cells have been comprehensively analyzed for SoC scaling through system-technology co-optimization. SRAM plays an integral role in the performance of SoCs, and the performance can be improved by SRAM on logic integration. Compared with one-tier BG SRAM cell design, the proposed monolithic three-tier BG SRAM cell releases the impact of metal line resistance and shows a 44.3% reduction in cell area, 28.4% improvement in read access time, 21.3% improvement in dynamic energy, and 43.6% improvement in energy-delay product. The energy- and area-efficient three-tier BG SRAM cell enables intelligent functionalities for the area- and energy-constrained edge computing devices.

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs.

The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.

(Invited) 3D Neural Network: Monolithic Integration of Resistive-RAM Array with Oxide-Semiconductor FET

1. Introduction In-memory computing has attracted worldwide attention for deep learning applications because of its high energy efficiency by implementing neural networks of deep learning in the form of memory array with computational function [1]. In particular, Resistive-RAM (RRAM)-based neural network [6,7] has been extensively studied from device to system level [2-4]. Binary neural network (BNN) has been proposed for its simple implementation in digital hardware [5]. RRAM-based BNN has advantages such as stability, noise margin, and testability. One challenge of BNN is the network size. Because of the low expression ability of binary weight and activation, the network size needs to be sufficiently large. For massive parallel input/output, 2D neural net suffers from large energy and delay in long interconnect wires. 3D neural network is a new technology direction enabling area-efficient, low-power, and low-latency computing (Fig. 1). For RRAM array, 1T1R cell is the most robust structure. XNOR operation, which is a basic computing element in BNN, can be efficiently implemented by 1T1R cell. To stack 1T1R RRAM array in 3D, access transistor needs to be fabricated by low-temperature BEOL-compatible process. The access transistor also has to drive sufficiently high current for RRAM cell. Oxide semiconductor such as IGZO is a promising channel material for this purpose [8-10]. In this work, we propose and develop a monolithic integration of RRAM array with IGZO access transistor in 3D stack. Then we demonstrate basic functionality of in-memory computing in the 3D neural net. The impact of the bit error rate of RRAM to the recognition accuracy of BNN is examined. 2. Device structure and fabrication process For typical multi-layer neural network, the output of each layer is connected to the input of next layer. In 3D neural network, the efficient interconnect and interface can be realized by rotating neighboring layer by 90o. Therefore, we propose spiral 3D stacking architecture of RRAM array. In each layer, IGZO FET is formed by bottom gate structure and HfO2 gate insulator. RRAM is formed in the stack of TiN/Ti/HfO2/TiN [11]. The process of 1T1R RRAM array is repeated 3 times. 3. Device characteristics of 3D RRAM array stack and im-memory computing operation We characterized IGZO FET and RRAM. Fig. 2(a) and (b) show the top/cross sectional images and Id-Vg curves of IGZO FET for all layers. Each layer shows almost identical characteristics. Normally-off operation, nearly ideal subthreshold slope, and >200μA drive current were obtained. Fig. 2(c) shows I-V curves of 1T1R cell for each layer. In measurement, IGZO access transistor is used to set compliance current. Nearly the same memory characteristics was obtained with the on/off ratio of >10. Endurance and retention characteristics were also examined and no reliability degradation was found by 3D integration. Note that because of the relatively large resistance of IGZO access transistor to RRAM cell, reset voltage is larger than that measured without access transistor. It is important to improve channel mobility of access transistor for low voltage and low power operation [12]. We demonstrate XNOR operation by using a pair of 1T1R cells in the fabricated chip as showing Fig. 3 (a). We choose voltage sensing scheme [7,13]. Weight bit (W) is complementarily written on RRAMs (R, R’). Input bit (x) is complementarily applied on word lines (VWL, VWL’). Bit line (BL) is precharged. Then, BL is discharged with slow or fast speed depending on the input and weight bit. After certain period of time, BL voltage is compared with reference voltage. The output bit (y) of XNOR is obtained from the comparator. The operation is performed by using the external peripheral circuit. Fig. 3(b) shows the waveforms and confirmed XNOR operation. XNOR output is digitally counted [5] or aggregated in voltage sensing at each BL [7] for weighted sum calculation.Based on the RRAM-based XNOR, we estimate the recognition accuracy of MNIST dataset in BNN using the framework in Fig.4(a). As shown in Fig. 4(b), although the accuracy is degraded as RRAM bit error rate (BER) increases, it is not very sensitive to BER up to certain level (10ppm in this case), which indicates the property of error-resilience in BNN. 4. Summary We developed a monolithic 3D integration of RRAM array with IGZO access transistor in 3D stack, confirmed each layer has uniform and almost identical device characteristics without degradation, and demonstrated functionality of in-memory computing and error-resilient BNN for 3D neural net. Acknowledgement This work was supported by JST CREST (16815651), JSPS KAKENHI Grant Number JP18H01489 and Tokyo Electron Ltd. Figure 1

Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation.

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm−3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.

(Invited) Epitaxial Growth of Ge/III-V Films and Hetero-Layer Lift-off for Ultra-Thin GeOI Fabrication

Ge have been considered as an alternative channel material to Si as well as a promising base material for optical components, adding new functions into current Si-LSI. It is necessary to form high quality Ge layers onto Si substrate for realization of Si/Ge monolithic 3D (M3D) devices. Combing high quality hetero-epitaxial growth of Ge/III-V semiconductors, low-temperature bonding, and an advanced lift-off technique, we have achieved Ge layer transfer on Si substrate, possessing excellent Ge crystallinity and electrical properties. The advanced HEtero-Layer-Lift-Off (HELLO) technique utilizing SiGe-based hetero-epitaxy and dozens digital etching (DDE) processes are demonstrated to realize high quality and ultra-thin Ge-on-insulator (GeOI) structures for ultimately scaled CMOS devices on Si platform.

A multi-walled carbon nanotubes coated 3D printed anode developed for Biophotovotaic applications

We report a method for the design and fabrication of 3D printed bioanodes for Biophotovotaic (BPV) applications. Electrodes were fabricated in 5 different thicknesses, from 0.2 mm to 1.0 mm with a 0.2 mm increment and the electrodes were coated with multi-wall carbon nanotubes (MWCNTs). Electrochemical characterisation of these electrodes was performed and the performance tested alongside a bare carbon paper electrode in a bespoke designed membrane electrode assembly (MEA)-type BPV device.All of the MWCNTs-coated 3D printed electrodes outperformed the bare carbon paper electrode. The best performing one (1.0 mm) showed a 40 times increment in power density and a 20 times reduction of the internal resistance. The successful development of the 3D printed bioanode can be used as a standardised platform for the comparison of similar materials. The development of the electrodes and MEA-type BPV device will serve as the initial step towards the development of a monolithic 3D printed BPV platform.

Advances in Design and Test of Monolithic 3-D ICs

Monolithic 3-D (M3D) technology enables unprecedented degrees of integration on a single chip. The miniscule monolithic intertier vias (MIVs) in M3D are the key behind higher transistor density and more flexibility in designing circuits compared to conventional through silicon via (TSV)-based architectures. This article presents a comprehensive design and test techniques for emerging M3D-enabled circuits and systems.