(Invited) 3D Neural Network: Monolithic Integration of Resistive-RAM Array with Oxide-Semiconductor FET

Abstract

1. Introduction In-memory computing has attracted worldwide attention for deep learning applications because of its high energy efficiency by implementing neural networks of deep learning in the form of memory array with computational function [1]. In particular, Resistive-RAM (RRAM)-based neural network [6,7] has been extensively studied from device to system level [2-4]. Binary neural network (BNN) has been proposed for its simple implementation in digital hardware [5]. RRAM-based BNN has advantages such as stability, noise margin, and testability. One challenge of BNN is the network size. Because of the low expression ability of binary weight and activation, the network size needs to be sufficiently large. For massive parallel input/output, 2D neural net suffers from large energy and delay in long interconnect wires. 3D neural network is a new technology direction enabling area-efficient, low-power, and low-latency computing (Fig. 1). For RRAM array, 1T1R cell is the most robust structure. XNOR operation, which is a basic computing element in BNN, can be efficiently implemented by 1T1R cell. To stack 1T1R RRAM array in 3D, access transistor needs to be fabricated by low-temperature BEOL-compatible process. The access transistor also has to drive sufficiently high current for RRAM cell. Oxide semiconductor such as IGZO is a promising channel material for this purpose [8-10]. In this work, we propose and develop a monolithic integration of RRAM array with IGZO access transistor in 3D stack. Then we demonstrate basic functionality of in-memory computing in the 3D neural net. The impact of the bit error rate of RRAM to the recognition accuracy of BNN is examined. 2. Device structure and fabrication process For typical multi-layer neural network, the output of each layer is connected to the input of next layer. In 3D neural network, the efficient interconnect and interface can be realized by rotating neighboring layer by 90o. Therefore, we propose spiral 3D stacking architecture of RRAM array. In each layer, IGZO FET is formed by bottom gate structure and HfO2 gate insulator. RRAM is formed in the stack of TiN/Ti/HfO2/TiN [11]. The process of 1T1R RRAM array is repeated 3 times. 3. Device characteristics of 3D RRAM array stack and im-memory computing operation We characterized IGZO FET and RRAM. Fig. 2(a) and (b) show the top/cross sectional images and Id-Vg curves of IGZO FET for all layers. Each layer shows almost identical characteristics. Normally-off operation, nearly ideal subthreshold slope, and >200μA drive current were obtained. Fig. 2(c) shows I-V curves of 1T1R cell for each layer. In measurement, IGZO access transistor is used to set compliance current. Nearly the same memory characteristics was obtained with the on/off ratio of >10. Endurance and retention characteristics were also examined and no reliability degradation was found by 3D integration. Note that because of the relatively large resistance of IGZO access transistor to RRAM cell, reset voltage is larger than that measured without access transistor. It is important to improve channel mobility of access transistor for low voltage and low power operation [12]. We demonstrate XNOR operation by using a pair of 1T1R cells in the fabricated chip as showing Fig. 3 (a). We choose voltage sensing scheme [7,13]. Weight bit (W) is complementarily written on RRAMs (R, R’). Input bit (x) is complementarily applied on word lines (VWL, VWL’). Bit line (BL) is precharged. Then, BL is discharged with slow or fast speed depending on the input and weight bit. After certain period of time, BL voltage is compared with reference voltage. The output bit (y) of XNOR is obtained from the comparator. The operation is performed by using the external peripheral circuit. Fig. 3(b) shows the waveforms and confirmed XNOR operation. XNOR output is digitally counted [5] or aggregated in voltage sensing at each BL [7] for weighted sum calculation.Based on the RRAM-based XNOR, we estimate the recognition accuracy of MNIST dataset in BNN using the framework in Fig.4(a). As shown in Fig. 4(b), although the accuracy is degraded as RRAM bit error rate (BER) increases, it is not very sensitive to BER up to certain level (10ppm in this case), which indicates the property of error-resilience in BNN. 4. Summary We developed a monolithic 3D integration of RRAM array with IGZO access transistor in 3D stack, confirmed each layer has uniform and almost identical device characteristics without degradation, and demonstrated functionality of in-memory computing and error-resilient BNN for 3D neural net. Acknowledgement This work was supported by JST CREST (16815651), JSPS KAKENHI Grant Number JP18H01489 and Tokyo Electron Ltd. Figure 1