Modified Gate Diffusion Input Research Articles

Design and Optimization of Reversible Arithmetic Unit Using Modified Gate Diffusion Input Logic

ABSTRACTIncreasing integration levels and demand for portability have made minimising the power consumption of circuits increasingly important for wide range of applications. Reversible logic is a low-power, low-loss design that can be utilised in low power CMOS, optical computing, nanotechnology, and quantum computing. Quantum machine learning Research is an area examines combining ideas from quantum computing and machine learning. In this paper, a new design of reversible logic-based arithmetic unit is demonstrated with CMOS and modified-GDI (MGDI) methodology for nanoscales using reversible gates. We provide a design for an optimized arithmetic unit, as well as some proposed methodologies for designing a reversible arithmetic unit with novel reversible gates, and compare them to existing circuits in terms of garbage output, constant input, number of reversible gates, and quantum cost, in this work. It can also be employed in Quantum computers due to its lower Quantum Cost and Garbage Output. Transistor-level implementations of the proposed arithmetic units are accomplished using Cadence Virtuoso tool GPDK 90 nm technology in combination with CMOS and MGDI techniques. Due to the optimization, the proposed arithmetic unit shows better performance in worst-case delay and power consumption than a comparable non-optimized Arithmetic Unit. According to the design and analysis of proposed Arithmetic Units. The proposed −1 design of the 4-bit Arithmetic Unit achieves optimisation by incorporating a reduced number of reversible gates and exhibiting a low quantum cost (12&40) using MGDI-FS. Similarly, the proposed −2 and 3 designs minimizes the number of transistors required, with a count of 80 and 120, and proposed −3 design, it eliminates the presence of constant inputs entirely using MGDI-FS.

Performance Enhancement of CNFET-based Approximate Compressor for Error Resilient Image Processing

The approximate computing has emerged as an appealing approach to minimize energy consumption. By implementing inexact circuits at the transistor level, significant enhancements in various performance metrics such as power consumption, delay, energy, and area can be achieved. Consequently, researchers worldwide have been actively exploring the application of inexact techniques in circuit design. This paper introduces a novel technique for designing low-power digital circuits called extremely low power modified gate diffusion input (ELP-MGDI). This technique combines the principles of Modified Gate Diffusion Input with the utilization of Carbon Nano Tube Field-Effect Transistors (CNTFETs). The Objective of this paper is to enhance the power, delay, and area characteristics of a 4:2 compressor and multiplier by employing ELP-MGDI approach. To achieve this, we conducted thorough analysis and simulations using the Verilog-A simulator 32 nm CNFET technology Stanford University within the Cadence Virtuoso Tool. The results show extremely power, delay reduction and power-delay-product (PDP) of approximate multiplier has been improved by over 99%, and the circuit area has been reduced by 55%. The proposed processing module demonstrates superior performance compared to their conventional counterparts.

A High-Performance Full Adder Design with Low Area, Power and Delay

A new one-bit adder architecture is described that may be used with a variety of logics, including Static CMOS, transmission gates, the Transmission Full Adder (TFA), and the New-14T Gate Diffusion Input Method (GDI). The Modified Gate Diffusion Input Method (MGDI) is used to suggest a novel structure design for a full adder. The full adder circuit is used in the Modified Gate Diffusion Input Method (MGDI), and experimental results demonstrate its superior performance compared to traditional methods. Full adders with multistage arrangements are also considered, as their performance may differ from that of a 1-bit full adder. As a result, two applications of multistage full adder structures, the ripple carry adder (RCA) and 6:2 compressor are used to analyze the findings. The power, area and delay are reduced by around 40% when compared to the existing methods. All the designs are simulated using Tanner EDA. The proposed full adder has a lower transistor count (6 or 7 transistors), lower power dissipation, and less delay than previous designs, according to simulation data.

Design of FinFET based low power, high speed hybrid decoder for SRAM

This paper proposes a novel FinFET based hybrid logic design for line decoders, which comprises of transmission gate logic (TGL), modified gate diffusion input (MGDI) logic and conventional NAND based FinFET logic. The 2–4 FinFET based decoder is designed using two topologies: (i) a 14- transistor topology for low power dissipation and lesser area and (ii) a 15-transitor topology for high-speed performance. Using the two topologies mentioned above, both inverting and non-inverting decoders of size 2–4 and 4–16 are designed. SPICE simulations of the proposed decoders are done at 45 nm CMOS and FinFET technologies and compared with different logic styles such as conventional logic, MGDI, mixed logic, and mixed MGDI logic at different frequencies with varying supply voltages and the proposed design outperforms other logic styles compared. The proposed FinFET hybrid decoder exhibits 6% and 77% lower power; 11.6% and 61.26% lower delay; 17% and 91.10% lower PDP respectively compared to the FinFET mixed decoder and CMOS hybrid decoder.

Design of Low Power and Area Efficient 8 Bit USR Using mGDI Technology

Technology is growing at a faster rate after the evolution of VLSI, which mainly focuses on three major criteria-speed, area and power. All these criteria determine the compactness of a product in order to produce an efficient output at a higher rate by consuming less power. To achieve the above-mentioned factors, an efficient 8-bit Universal Shift Register (USR) has been designed using modified Gate Diffusion Input (mGDI) technique. The results have been simulated using the TANNER EDA tool and found to contribute for low power and area.

4-bit Carry Look Ahead Adder Using MGDI Technique

Abstract: Today's high-performance processor is built with arithmetic logic units that add and subtract key components. Design considerations related to low power and high performance digital VLSI circuits have become more prevalent in today's world. In order to develop low-power and high-performance processors, the designers need to design their adder circuits with the required speed and power dissipation for their applications. This topic introduces the concept of a adder using MGDI Technique. The Exact Speculative Carry Look Ahead Adder the use of the Modified-GDI (Modified-Gate Diffusion Input) is cautioned in this work. The delay, location and energy trade off performs a integral role in VLSI. We already comprehend that designs which are of CMOS fashion occupy extra area might also eat extra strength consumption. The switching conduct of the circuit reason the heating up of integrated circuits affects the working stipulations of the purposeful unit. The adders are the most important parts of countless applications such as microprocessors, microcontrollers and digital signal processors and additionally in actual time applications. Hence it is necessary to minimize the adder blocks to format a perfect processor. This work is proposed on a 16 bit carry seem to be in advance adder is designed through using MGDI gate and 4T XOR gates and a speculator blocks. The proposed MGDI raise Look Ahead adder occupies 68% much less region and the strength consumption and the propagation extend additionally considerably reduces when in contrast to the traditional carry Look Ahead adder why because the variety transistors extensively reduces from 1448 (Conventional) to 456 (Proposed CLA). The simulation consequences of the proposed format carried out in Xilinx. Keywords: Delay, power dissipation, voltage, transistor sizing.

Ultra-Low Power 8-Transistor Modified Gate Diffusion Input Carbon Nano-Tube Field Effect Transistor Full Adder

An ultra-low power 8-Transistor Modified Gate Diffusion Input (MGDI) Carbon Nano Tube Field Effect Transistor (CNTFET) Full Adder (FA) has been presented in this paper. The proposed 8-T MGDI CNTFET Full Adder outperforms other adders in terms of Power Consumption, Propagation Delay and the PDP at different levels of Power Supply and Temperatures. The power consumption of the proposed 10 nm CNTFET 8-T MGDI Full Adder at 27°C is 1.96 nW. The proposed CNTFET FA exhibits 60.32% improvement in Power Consumption when compared to the existing 10 nm FINFET 8-T MGDI Full Adder. The propagation Delay of the proposed FA is 42.16 ps and an improvement of 57.68% is noticed over the existing FA. The Power Delay Product of the proposed 10 nm CNTFET 8-T MGDI FA is 82.63 × 10−21 Jules, whereas the PDP of the 10 nm FINFET 8-T MGDI FA is 492.07 × 10−21 Jules. The PDP of the proposed 10 nm CNTFET 8-T MGDI Full Adder exhibits 83.21% improvement when compared to the 10 nm FINFET 8-T MGDI FA.

Design, Implementation and Performance Analysis of Test Pattern Generator for Built-In Self-Test using m-GDI Technology

Background: A Linear Feedback Shift Register (LFSR) is typically used for generating the test patterns in built-in self-test (BIST) as it produces pseudorandom patterns at every clock cycle. These pseudo-random patterns are used as test vectors for testing the VLSI circuits. Objective: The pseudorandom patterns generated by the LFSR exhibit low-correlation among the patterns, this increases the switching activity and power dissipation while testing the VLSI circuit. Thus, to reduce the testing power, modified gate diffusion input (m-GDI) logic based LFSR in 45nm technology is proposed in this paper. Methods: The circuits are developed on m-GDI technology using the Cadence virtuoso tool and a spectre simulator is used to carry out the simulation. Findings: Comparative analysis revealed that the delay and power are reduced significantly, for the proposed design when compared to the existing LFSRs in conventional CMOS, GDI and reversible logic. Novelty and applications: In conventional LFSR, an external source is necessary to load the seed value and it dissipates more power. But in the proposed design, the seed value is generated by the circuit itself. This reduces the power and critical path delay. Further a complete zero patterns is not possible in conventional LFSR design. But in proposed design, all zero pattern is plausible. The design obtained from this study can be applied in low-power, high-speed BIST circuits. Keywords: LFSR; Seed Value; Test Patterns; Built-In-Self-Test; m-GDI

A novel ultra-low power 7T full adder design using mixed logic

The key point is to design and implementation of the full adder which provides high-speed, Power efficiency and leas area with good voltage swing”.Where the term ‘Novel’ indicates that If something is so new, genuine and original that it had never been seen, used or even thought of before, call it is considered as ‘novel’ and ‘Ultra low power’ indicates that with the minimal amount of system power is enough for performing the respective operation of its own. In this article, a new High Performance and low power full adder utilizing a distinctive design "Mixed Logic Design" is recommended in implementation. The mixed - logic design combines Modified Gate diffusion input (MGDI) Transmission Gate Logic (TGL), Static CMOS logic, Pass transistor logic(PTL )and various logics which requires the recommended circuit. Full adder is a digital circuit which performs the sum of bits. In many PC’s and various kinds of microprocessors, adders are utilized in the ALU. The traditional Complementary Metal Oxide Semiconductor (CMOS) Full adder consisting of 28-Transistors and is built on a traditional Complementary Metal Oxide Semiconductor structure. GDI technique is low power and high-speed design technique where it takes 10 T.Gate Diffusion Input is one of the circuit design logics which occupies less area, simulates with high speed and power-efficient technique. It entails less count of transistors as correlated to traditional Complementary Metal Oxide Semiconductor technology. But the disadvantage with Gate Diffusion Input technique is that it provides an output having poor logic swing after simulation. The Modified-Gate diffusion input (MGDI ) technique rectifies this issue by implementing FA with 8T.But we are implementing another alternative “Mixed logic design” (combining the GDI, CMOS, TGL, etc logics ) and designing the Circuit with least count of transistors and compare with other unique logics which helps them to simulate the circuit in a power-efficient way and time delay.

WITHDRAWN: High performance IIR filter design with MOD-GDI based array multiplier

Abstract Due to an upsurge in technology, there is a need for development resemblance in portable devices besides its high speed and low power capability. The most critical factors are area, total power dissipation, and propagation delay to estimate a device's performance. Signal processing modules viz. Finite Impulse Response (FIR) or Infinite Impulse Response (IIR) filters are fundamental elementary logics in DSP systems. Performance optimization of a digital IIR filter is always trendy for VLSI DESIGN Engineers. We can also achieve by improving sub-modules' efficiency (like. adder, multiplier, and delay elements) required to realize the filter architecture. This paper aims to extract a layout of the IIR filter implemented using a high-speed 4-bit Array Multiplier. The multiplier for this IIR designed with Modified Gate Diffusion Input (MOD-GDI) technique reduces the additional circuitry, which reduces the area and average power dissipation of overall filter logic. Extracted the layout by using Mentor Graphics EDA tools (with 130 nm technology). Compared to the performance characteristics like area, delay, the power consumption of the proposed and conventional IIR filters. The proposed IIR filter is space-efficient and consumes less power than the traditional IIR filters.

New MGDI-based full adder cells for energy-efficient applications

ABSTRACT In this paper, we present two new logic schemes to implement full adder cell using XOR-XNOR and NOR gates. Gate diffusion input (GDI) and modified GDI (MGDI) cells help to design low power circuits using less number of transistors. In this work, we design two new NOR gates based on MGDI cell. Then, using one of them and MGDI XOR-XNOR gates, two low-power and energy-efficient full adders which also meet full-swing property are proposed. The performance of our new full adders is evaluated and compared with some of the familiar full adders. Post-Layout simulations using Cadence Virtuoso tools in TSMC 0.18 μm CMOS process technology are carried out and the results show almost 24%–56% (22%–55%) and 36%–66% (28%–62%) improvements in the features power consumption and power-delay product (PDP), respectively. Also, full-swing property of our new adders are proved when they are subjected to all possible input combinations and transitions.

Performance Analysis of Multipliers Using Modified Gate Diffused Input Technology

The primitive constraints in any VLSI system design are power, delay and area. Systems based on CMOS logic consume more power and area. Higher power dissipation will have a direct effect on the lifetime and performance of digital systems. Adders and multipliers form the core of almost all the digital systems like Microprocessor, Digital Signal Processors (DSPs), etc., so the adders and multipliers need to be optimized in terms of power, area and delay for an efficient and cost-effective processor design. This paper presents an approach for implementing 8-bit Array multiplier, Wallace Tree multiplier and Vedic multiplier using modified Gate Diffusion Input (m-GDI) technology and comparative analysis against area, power and delay. From the analysis, it is found that multipliers, which are built on m-GDI logic, occupy less area, dissipate less power and experience less delay than the multipliers based on CMOS logic, GDI logic and Booth multiplier. Also among the three m-GDI-based multipliers, Vedic multiplier performs better in terms of area, speed and power than array multiplier and Wallace tree multiplier.

Symmetric Stacking Based Fast Binary Counter Using Modified Gate Diffusion Input (M-GDI) Technique

In this paper, modified-Gate Diffusion Input (M-GDI) based binary counter is designed using symmetric stacking method. The binary counter is designed using 3-bit stacker circuit that groups the one bit together and symmetric method is used to form 6-bit stack. The 6-bit stack is converted to binary count to produce required counters. The M-GDI is used to further reduce the transistor count than the CMOS logic transistor count. Mainly the basic gates are developed using the M-GDI technique and the basic gates are replaced in the 6:3 counters to further improve counter-performance. The proposed 6:3 binary counter has no Exclusive or gate (XOR) gates on the critical path, which leads to faster performance of the circuit. The proposed counter is faster, also consumes less power than the traditional. By using this proposed counter in Wallace multiplier, the delay and power for higher-order multipliers is reduced. This paper proposes a novel symmetric stacking based fast binary counters using the modified gate diffusion input (M-GDI) technique. This paper proposes a novel binary counter.

High Speed, Low Area Exact Speculative Carry Look Ahead Adder using MGDI Technique

The Exact Speculative Carry Look Ahead Adder using the Modified-GDI (Modified-Gate Diffusion Input) is suggested in this work. The delay, area and power tradeoff plays a vital role in VLSI. We already know that designs which are of CMOS style occupy more space may consume more power consumption. The switching behavior of the circuit cause the heating up of integrated circuits affects the working conditions of the functional unit. The adders are the main parts of several applications such as microprocessors, microcontrollers and digital signal processors and also in real time applications. Hence it is important to minimize the adder blocks to design a perfect processor. This work is proposed on a 16 bit carry look ahead adder is designed by using MGDI gate and 4T XOR gates and a speculator blocks. The proposed MGDI carry Look Ahead adder occupies 68% less area and the power consumption and the propagation delay also drastically reduces when compared to the conventional carry Look Ahead adder why because the number transistors drastically reduces from 1448 (Conventional) to 456 (Proposed CLA). The simulation results of the proposed design implemented in Xilinx.

A Review On Modified Gate Diffusion Input Logic: An Approach For Area And Power Efficient Digital System Design

In recent days, the main motto of VLSI designers is to reduce the power and area as devices are becoming battery-operated, compact and require enhanced functionality and features. Due to the scaling and shrinking of devices, the transistor leakage power has increased at an exponential rate. In this paper, analysis on the research based on the Modified gate diffusion input technique (m-GDI) which has gained much attention in recent days are encompassed. Consequently, 31 research papers homologous to m-GDI technique are assessed and analysed based on the numerous targets. In this review, we present the m-GDI Technique, a low power technique and scrutinize the modern breakthroughs with several pros and cons. The thorough examination is done on finding the inclusion of the issues, methodologies, simulation tools and technologies used.

Efficient VLSI Architecture for 16-Point Discrete Cosine Transform

The Discrete Cosine Transform (DCT) is an important transform in image and video processing systems. The perception of human visualization permits us to be numerically approximate rather than exact with slight compromise in accuracy. In this paper, we have proposed a digital implementation of 16-point approximate DCT architecture based on Modified Gate Diffusion Input (MGDI) technique. The 8-point DCT architecture can be realized in digital Very Large Scale Integration (VLSI) hardware with only 12 additions. The proposed 8-transistor MGDI full adder is used instead of existing 10-transistor MGDI full adder in the DCT architecture. It results in reduced circuit complexity, power and delay. Approximate multiplier-free MGDI DCT is simulated in Tanner SPICE for 90-nm CMOS process technology at 100 MHz. The simulation result shows that 20%, 16% and 7% of area, power and delay are reduced, respectively, when compared with approximate DCT by using 14 additions. The performance was evaluated based on peak signal-to-noise ratio (PSNR), and the proposed architecture shows enhancement in terms of hardware complexity, regularity and modularity with a little compromise in accuracy.

Design of multiple-valued logic gates using gate-diffusion input for image processing applications

In this work, unique characteristics of carbon nano-tube field effect transistor (CNTFET) are used to propose a universal cell with a simple architecture based on the binary modified gate-diffusion input (m-GDI) method for designing fundamental gates in the voltage-mode multiple-valued logic (MVL) with any arbitrary number of logic levels for processing at nano-scales. The results of the simulations confirm more energy-efficiency, larger noise margins and lower sensitivity of the proposed designs in different logic levels as compared with the state-of-the-art designs. The effects of the process, voltage and temperature (PVT) variations are extensively evaluated by Monte–Carlo simulation. According to the results, the proposed designs are robust against PVT variations and noise. The proposed structure is applied to the MVL-based image processing. The results show that the output images of the proposed MVL-based inexact gates have an appropriate quality in compare with the images generated by the other similar exact gates.

A novel modified GDI method-based clocked M/S-TFF for future generation microprocessor chips in nano schemes

In this work, a novel architecture is proposed for designing the clocked master-slave TFF (M/S-TFF) based on modified gate-diffusion input (m-GDI) method. By noting that we used clocked phase scheme or feedback input technique in designing the M/S-TFF circuit. The advantages of the proposed scheme can be cited as reduce the number of required transistors, lower power consumption-propagation delay product (PDP) in all activity factors and layout area in comparison with similar state-of-the art designs. More importantly, Monte-Carlo simulations confirm proposed topology gains substantial variation tolerance with a substantial small standard deviation and considerable lower variability percentage in metrics than other schemes in same technology. At the end, the presented static frequency divider (SFD) using proposed M/S-TFF, works at wider frequency range with 0.198 milli-Watt (mW) power dissipation at the maximum operating frequency (fmax.) about 46 Giga-Hertz (GHz) under 0.9 Volt supply voltage. Therefore, using the proposed scheme can be improved in data storing elements, prescaler block in phase-locked loop (PLL) chips for future of generation communication networks like: fifth generation (5G) and microprocessors performance.

A 16-BIT HIGH-SPEED MULTIPLIER DESIGN BASED ON KARATSUBA ALGORITHM AND URDHVA-TIRYAGBHYAM THEOREM USING MODIFIED GDI CELLS FOR LOW POWER AND AREA CONSTRAINTS

The paper entails the design of a 16-bit multiplier with the combined application of Karatsuba algorithm and the Urdhva-Tiryagbhyam (UT) theorem and the implementation of the multiplier architecture in Modified-Gate-Diffusion-Input (Mod-GDI) cells for improving the area and power constraints in the proposed novel hybrid multiplier.

A novel design of low power and high read stability Ternary SRAM (T-SRAM), memory based on the modified Gate Diffusion Input (m-GDI) method in nanotechnology

The conventional complementary metal-oxide semiconductor (CMOS) design techniques confront to the limitation of designing the integrated circuits (ICs), especially memories, with multiple-valued logic (MVL) in nanotechnology. Gate diffusion input (GDI) technique, provides the possibility to design low power logic gates with small chip area and interconnection capacitors while the number of transistors is diminished. In this paper first ternary GDI (t-GDI) cell based on the proposed binary (two-valued) modified GDI (m-GDI) method, which is appropriate for designing circuits using MVL, is designed. Then, by using the standard ternary inverter (STI) gate implemented based on the proposed t-GDI cell with better noise margins and also small standard deviation of results, first novel design of a ternary SRAM (T-SRAM) cell is presented for nano process, which has smaller standby power dissipation and standard deviation for delay of writing and reading cycles, better read static noise margin (RSNM) and lower signal control complexity. The design of specific structure of 4-words×4-bits, ternary SRAM (4×4 T-SRAM) shows that the number of connections, chip area is decreased and power-delay product (PDP) criterion is improved for writing and reading cycles with significant small standard deviation in compare with the other similar T-SRAMs designed.The effects of different process variations such as density, number of CNTs and temperature variations are extensively evaluated by Monte-Carlo simulation, with respect to performance metrics such as delay, power dissipation and PDP of writing and reading cycles, also RSNM parameter for SRAM cells. The comparison exhibits that in all cases the proposed T-SRAM cell showing a substantial small standard deviation and considerable lower variability percentage than state-of-the art SRAM cells. So, the proposed T-SRAM cell design has the lowest sensitivity variations, thus it is an attractive choice for nano technology application in the presence of impact process and temperature variations. The simulation is done with Synopsys H-SPICE simulator in 32nm technology under the condition of variations.