Modified Gate Diffusion Input Research Articles

A novel modified GDI method-based clocked M/S-TFF for future generation microprocessor chips in nano schemes

In this work, a novel architecture is proposed for designing the clocked master-slave TFF (M/S-TFF) based on modified gate-diffusion input (m-GDI) method. By noting that we used clocked phase scheme or feedback input technique in designing the M/S-TFF circuit. The advantages of the proposed scheme can be cited as reduce the number of required transistors, lower power consumption-propagation delay product (PDP) in all activity factors and layout area in comparison with similar state-of-the art designs. More importantly, Monte-Carlo simulations confirm proposed topology gains substantial variation tolerance with a substantial small standard deviation and considerable lower variability percentage in metrics than other schemes in same technology. At the end, the presented static frequency divider (SFD) using proposed M/S-TFF, works at wider frequency range with 0.198 milli-Watt (mW) power dissipation at the maximum operating frequency (fmax.) about 46 Giga-Hertz (GHz) under 0.9 Volt supply voltage. Therefore, using the proposed scheme can be improved in data storing elements, prescaler block in phase-locked loop (PLL) chips for future of generation communication networks like: fifth generation (5G) and microprocessors performance.

A 16-BIT HIGH-SPEED MULTIPLIER DESIGN BASED ON KARATSUBA ALGORITHM AND URDHVA-TIRYAGBHYAM THEOREM USING MODIFIED GDI CELLS FOR LOW POWER AND AREA CONSTRAINTS

The paper entails the design of a 16-bit multiplier with the combined application of Karatsuba algorithm and the Urdhva-Tiryagbhyam (UT) theorem and the implementation of the multiplier architecture in Modified-Gate-Diffusion-Input (Mod-GDI) cells for improving the area and power constraints in the proposed novel hybrid multiplier.

A novel design of low power and high read stability Ternary SRAM (T-SRAM), memory based on the modified Gate Diffusion Input (m-GDI) method in nanotechnology

The conventional complementary metal-oxide semiconductor (CMOS) design techniques confront to the limitation of designing the integrated circuits (ICs), especially memories, with multiple-valued logic (MVL) in nanotechnology. Gate diffusion input (GDI) technique, provides the possibility to design low power logic gates with small chip area and interconnection capacitors while the number of transistors is diminished. In this paper first ternary GDI (t-GDI) cell based on the proposed binary (two-valued) modified GDI (m-GDI) method, which is appropriate for designing circuits using MVL, is designed. Then, by using the standard ternary inverter (STI) gate implemented based on the proposed t-GDI cell with better noise margins and also small standard deviation of results, first novel design of a ternary SRAM (T-SRAM) cell is presented for nano process, which has smaller standby power dissipation and standard deviation for delay of writing and reading cycles, better read static noise margin (RSNM) and lower signal control complexity. The design of specific structure of 4-words×4-bits, ternary SRAM (4×4 T-SRAM) shows that the number of connections, chip area is decreased and power-delay product (PDP) criterion is improved for writing and reading cycles with significant small standard deviation in compare with the other similar T-SRAMs designed.The effects of different process variations such as density, number of CNTs and temperature variations are extensively evaluated by Monte-Carlo simulation, with respect to performance metrics such as delay, power dissipation and PDP of writing and reading cycles, also RSNM parameter for SRAM cells. The comparison exhibits that in all cases the proposed T-SRAM cell showing a substantial small standard deviation and considerable lower variability percentage than state-of-the art SRAM cells. So, the proposed T-SRAM cell design has the lowest sensitivity variations, thus it is an attractive choice for nano technology application in the presence of impact process and temperature variations. The simulation is done with Synopsys H-SPICE simulator in 32nm technology under the condition of variations.

Area and Power Efficient VLSI Architecture for Two Dimensional 16-point Modified Gate Diffusion Input Discrete Cosine Transform

The two-dimensional (2D) Discrete Cosine Transform (DCT) is used widely in image and video processing systems. The perception of human visualization permits us to design approximate rather than exact DCT. In this paper, we propose a digital implementation of 16-point approximate 2D DCT architecture based on one-dimensional (1D) DCT and Modified Gate Diffusion Input (MGDI) technique. The 8-point 1D Approximate DCT architecture requires only 12 additions for realization in digital VLSI. Additions can be performed using the proposed 8 transistor (8T) MGDI Full Adder which reduces 2 transistors than the existing 10 transistor (10T) MGDI Full Adder. The Approximate MGDI 2D DCT using 8T MGDI Full adders is simulated in Tanner SPICE for 0.18㎛ CMOS process technology at 100MHZ.The simulation result shows that 13.9% of area and 15.08 % of power is reduced in the 8-point approximate 2D DCT, 10.63 % of area and 15.48% of power is reduced in case of 16-point approximate 2D DCT using 8 Transistor MGDI Full Adder than 10 Transistor MGDI Full Adder. The proposed architecture enhances results in terms of hardware complexity, regularity and modularity with a little compromise in accuracy.

Design of low power and high read stability 8T-SRAM memory based on the modified Gate Diffusion Input (m-GDI) in 32 nm CNTFET technology

SRAM designing with greater storage capacity and lower power dissipation with desired stability by employing conventional CMOS technology seems to be impossible due to enhancement of short channel effect and leakage current due to increasing the number of the transistors. Up to now a lot of methods have been proposed in order to improve the performance of the logical circuits based on the CMOS technology, among of them the Gate-Diffusion Input (GDI) technique is an efficient method. In this paper the modified GDI cell (m-GDI) based on the basic GDI cell is proposed and then SRAM cell memory with 8 transistors (8T-SRAM) which uses the proposed GDI cell is presented.Due to the achieved results the stability-power dissipation ratio (SPR), the evaluation parameter in SRAM memories, is improved about 7 for 8T-SRAM which is implemented with a stack forcing method in similar carbon nanotube field-effect transistor (CNTFET) technology.Finally the 4×4 SRAM memory is proposed based on 1×1 SRAM with the help of 8T-SRAM. This memory is presented with array structures for reading and writing blocks.The simulation results reveal that the Power-Delay Product (PDP) term decreases 18% and 36% in the reading and writing cycles respectively for the stack forcing SRAM with the same array.The simulation is done with H-SPICE software in 32nm technology under the condition of 0.9V supply voltage, 500MHz frequency and room temperature.

Modified Gate Diffusion Input Technique: A New Technique for Enhancing Performance in Full Adder Circuits

Addition is an indispensable operation for any high speed digital system, digital signal processing or control system. The primary issues in the design of adder cell are area, delay and power dissipation. Optimization of several devices for speed and power is a significant issue in low-voltage and low-power applications. These issues can be overcome by incorporating Gated Diffusion Input (GDI) technique. This paper mainly presents the design of 5 different full adder topologies using Modified Gate Diffusion Input Technique. This technique allows reducing power consumption, delay and area of digital circuits, while maintaining low complexity of logic design. This paper focuses two main design approaches. The former presents the implementation of modified primitive logic cells and its performance issues were compared with GDI and CMOS logic. The latter presents the implementation of 5 different modified GDI full adders and its performance issues. The simulation results reveal better delay and power performance for the proposed modified GDI full adders when compared with the existing GDI technique, CMOS and pass transistor logic at 0.250μm CMOS technologies. Delay and power has been evaluated by Tanner simulator using TSMC BSIM 0.250μm technologies.