Performance Analysis of Multipliers Using Modified Gate Diffused Input Technology

Abstract

The primitive constraints in any VLSI system design are power, delay and area. Systems based on CMOS logic consume more power and area. Higher power dissipation will have a direct effect on the lifetime and performance of digital systems. Adders and multipliers form the core of almost all the digital systems like Microprocessor, Digital Signal Processors (DSPs), etc., so the adders and multipliers need to be optimized in terms of power, area and delay for an efficient and cost-effective processor design. This paper presents an approach for implementing 8-bit Array multiplier, Wallace Tree multiplier and Vedic multiplier using modified Gate Diffusion Input (m-GDI) technology and comparative analysis against area, power and delay. From the analysis, it is found that multipliers, which are built on m-GDI logic, occupy less area, dissipate less power and experience less delay than the multipliers based on CMOS logic, GDI logic and Booth multiplier. Also among the three m-GDI-based multipliers, Vedic multiplier performs better in terms of area, speed and power than array multiplier and Wallace tree multiplier.