Implemenation and Analysis of Different 32-Bit Multipliers on Aspects of Power, Speed and Area

Abstract

VLSI is a domain that is constantly pushing the boundaries in the field of logical devices by striving to get greater compute power from reduced device area by composition of high number of logical devices onto ever decreasing areas. It is well known that multipliers consume most of the power in DSP computations. It is of utmost importance for modern DSP systems to come up with multipliers that consume low power to reduce the power dissipation without needing to compromise on speed and area. This paper talks about the implementation of four different 32-bit multiplier architectures and the comparison of the speed, area and power of the multipliers and their applications. The four multipliers being considered are Booth multiplier, Wallace Tree Multiplier, Vedic Multiplier and Dadda multiplier. The Multipliers are designed and implemented using Verilog and synthesised using Xilinx ISE tool. A Wallace tree multiplier is the improved version of tree-based multiplier architecture. It uses the Carry-Save addition algorithm to reduce the latency. Many modifications and new techniques are being worked upon to enhance speed of the standard Booth Multiplier. Vedic multiplier is built on the foundation of Vedic mathematics. It is an area that's drawing wide interest and focus due to its capabilities of being a low power multiplier combined with faster compute speed. There are sixteen sutras in Vedic multiplication in which “Urdhva Tiryakbhyam” has been noticed to be the most efficient one in terms of speed. Dadda multiplier does the minimum reduction necessary at each level to perform the reduction in the same number of levels as required by a Wallace tree multiplier it exhibit similar delay.