Investigation and Analysis of Power Performance Area (PPA) Cards of Digital Multiplier Architectures

Abstract

The crucial role played by digital multipliers in VLSI system design makes it indispensable to study the PPA cards of digital multiplier architectures before tailoring multiplier architecture into such systems. Therefore, in this work, we present a detailed investigation and analysis of PPA cards of popular digital multiplier architectures, for various wordlengths. Each multiplier has been implemented on Artix-7 FPGA xc7a200tfbg676-2 and analyzed using Xilinx Vivado Design Suite 2019.2. A major contribution in this paper is the study of energy profiles of the architectures, not focused on in the earlier literature. This study compares their device utilization, timing parameters, power consumption, and energy profiles. Results indicate that Dadda Tree Multiplier and Wallace Tree Multiplier (460 slices and 557 slices, respectively, for [Formula: see text] bits) are undoubtedly the least slices consuming fast multipliers, but their power consumption and energy density are high as well. For 32-bit implementation, Vedic Multiplier consumes 48.9% lower power than Dadda Tree Multiplier, while the latter occupies 30.42% lesser slices. The speed of the Vedic Multiplier is in close proximity with the tree multipliers. The energy density of Vedic Multiplier (0.3[Formula: see text]nJ/slice) is much lower than that of Dadda Tree Multiplier (0.77[Formula: see text]nJ/slice).