Field-effect Transistor Model Research Articles

Batch-Fabricated WSe₂-on-Sapphire Field-Effect Transistors Grown by Chemical Vapor Deposition

Stepper-based batch fabrication of top-gated field-effect transistors (FETs) is demonstrated on few-layer WSe2-on-sapphire grown by chemical vapor deposition. This article reports the electrical characterization of 94 transistors with three different transistor structures. ON-/ OFF-current ratios exceeding 105 at room temperature with noise-floor-limited gate current and contact-limited ON-current density of 15 nA/ $\mu \text{m}$ was achieved for FETs using a structure in which the gate overlaps the source and drain contacts. Two transistors with open channel access regions are used to allow ion doping through polyethylene oxide: cesium perchlorate (PEO: CsClO4) to induce electron and hole conductivity and allow characterization of the intrinsic FET characteristics. In these geometries, the ON-current increased by four orders of magnitude with ON-/ OFF-current ratio greater than 106 at ${V}_{\text {DS}} = -0.05$ V, compared to gate overlapped FETs. An analytic 2-D FET model was used to model the full current-voltage characteristics. This allowed the field-effect mobility to be extracted revealing the gate and drain field dependence for the first time. The fit of the measured characteristics from subthreshold to saturation is made with only four fitting parameters, revealing a field-dependent electron mobility ranging from 1 to 2.6 cm2/Vs.

Quantitative, experimentally-validated, model of MoS2 nanoribbon Schottky field-effect transistors from subthreshold to saturation

We investigate the channel length dependence of the electrical characteristics of chemical vapor transport (CVT)-grown MoS2 nanoribbon (NR) Schottky barrier field-effect transistors to provide insights into the transport properties of such nanostructures. The MoS2 NRs form spontaneously during the CVT growth, without the application of etching. Back gated transmission line measurement FETs were fabricated on a 45μm-long NR with channel lengths ranging between 200 nm and 3μm. Contact and sheet resistances were extracted from the electrical measurements and their back-gate bias dependence was analyzed. Numerical modeling based on a virtual probe approach combined with the Landauer formalism shows excellent agreement with the measurements. The model enables a quantitative extraction of the intrinsic FET properties, e.g., mean-free-path and electron mobility, and their dependence on carrier density and investigation of plausible trap distributions. A record electron mobility for a MoS2 NR channel of ∼81cm2/Vs was achieved.

A Compact Short-Channel Analytical Drain Current Model of Asymmetric Dual-Gate TMD FET in Subthreshold Region Including Fringing Field Effects

A compact drain current model is developed for an asymmetric, dual gate, monolayer 2 - D Transition metal dichalcogenide (TMD) field effect transistor (FET) in the subthreshold region. The work includes the effect of source to drain tunneling and gate dielectric fringing effects. The model is systematically derived for an asymmetric, dual gate structure. The model developed is also extended into a dual-gate symmetric structure. The characteristic length expression has only physical and dimensional parameters including the contribution of fringing field effects from both front and back gate dielectric. The model is validated with simulation results obtained using NEGF based nanodevice simulators and experimental data of WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> p-channel FET. Also, transfer characteristics, output characteristics, subthreshold swing and output resistance are compared with reported data in literatures. A close agreement is observed with some disparity arising because of the non-inclusion of back gate fringing effects and source to drain tunneling in their models. The proposed model captures the effects of different high-κ gate dielectric materials and its thicknesses. Impact of temperature is also studied on transfer characteristics. The model is also scalable from ultrashort channel regime to long channel regime. Finally, the model can be applicable not only for TMD materials but other 2 - D materials also.

Analytical Current Transport Modeling of Monolayer Molybdenum Disulfide-Based Dual Gate Tunnel Field Effect Transistor

In this paper, we present a current transport model of MoS2-based dual gate tunnel field effect transistor from both analytical and numerical techniques. In analytical modeling, two-dimensional (2D) model of potential distribution with its corresponding energy level for the hetero-junction has been solved and implemented with Landauer current transport mechanism. The output characteristics have been compared with the quantum mechanical solution obtained from non-equilibrium Green's function (NEGF) formalism. The sub-threshold slope (SS), obtained from analytical and NEGF methods are 10 mV/decade and 12.6 mV/decade with on/off current ratio of 107 and 106, respectively at VDS = 0.5 V. We have considered scattering mechanism into our calculation and have shown that carrier transportation for 20 nm channel length is diffusive. In addition, scattering reduces the on current by an order of magnitude, and resembles good agreement with the atomistic simulation. Lastly, mobility and ionized impurity concentration for our proposed structure have been calculated as 27.2 cm2/Vs and 1.17 × 1013/cm2.

Thermal Noise Models for Trigate Junctionless Transistors Including Substrate Bias Effects

Thermal noise power spectral density (PSD) models for trigate junctionless field-effect transistors (TG-JLFETs) incorporating substrate bias effects are developed in this article. The PSDs of drain current thermal noise, induced gate noise, and cross correlation between the two noises are derived for TG-JLFET using the modified Klaassen and Prins (KP) equation. An all-region drain current model of TG-JLFET is used to obtain the aforementioned thermal noises. Thermal noise PSD in TG-JLFET depends on channel conductance, and substrate bias voltage significantly modulates the channel conductance, and thus, the substantial impact of substrate bias can be observed on thermal noise of TG-JLFET. Model results are validated with the simulation results obtained using a 3-D technology computer-aided design (TCAD)-based device simulator from Synopsys.

Advances in Compact Modeling of Organic Field-Effect Transistors

In this review, recent advances in compact modeling of organic field-effect transistors (OFETs) are presented. Despite the inherent strength for printed flexible electronics and the extremely aggressive research conducted over more than three decades, the OFET technology still seems to remain at a relatively low technological readiness level. Among various possible reasons for that, the lack of a standard compact model, which effectively bridges the device- and system-level development, is clearly one of the most critical issues. This article broadly discusses the essential requirements, up-to-date progresses, and imminent challenges for the OFET compact device modeling toward a universal, physically valid, and applicable description of this fast-developing technology.

High-Frequency Performance Study of CNTFET-Based Amplifiers

This article details the design of single- and double-stage maximum gain and low-noise high-frequency amplifiers at 2.4 GHz using a compact carbon nanotube field-effect transistor model, which is initially calibrated with hysteresis-free experimental data from a technology suitable for high-frequency applications. Parameters of the compact model represent CNTFETs with maximum high-frequency gain and reduced high-frequency noise by eliminating the metallic tubes contribution. Studies on linearity of the amplifiers as well as the impact of the quality factor of the inductors used in the stabilization network and the density of the nanotubes on amplifier performance are presented. Results of RF amplifiers show that CNTFETs are credible contenders for developing applications in S-band because of their gain (around 12 dB for a double-stage gain design), low noise ( $NF_{\rm {min}}$ = 1.5 dB for a single-stage LNA) and linearity performance (OIP $_{3}$ around 15 dBm for a single-stage gain amplifier design).

Modeling of Total Ionizing Dose Degradation on 180-nm n-MOSFETs Using BSIM3

This paper presents a modeling approach to simulate the impact of total ionizing dose (TID) degradation on low-power analog and mixed-signal circuits. The modeling approach has been performed on 180-nm n-type metal–oxide–semiconductor field-effect transistors (n-MOSFETs). The effects of the finger number, channel geometry, and biasing voltages have been tested during irradiation experiments. All Berkeley short-channel insulated gate field-effect transistor model (BSIM) parameters relevant to the transistor properties affected by TID have been modified in an algorithmic flow to correctly estimate the sub-threshold leakage current for a given dose level. The maximum error of the model developed is below 8%. A case study considering a five-stage ring oscillator is simulated with the generated model to show that the power consumption of the circuit increases and the oscillation frequency decreases around by 14%.

Simulation Program with Integrated Circuit Emphasis Compact Modeling of a Dual-Gate Positive-Feedback Field-Effect Transistor for Circuit Simulations.

In this work, we developed a SPICE compact model of a dual-gate positive-feedback field-effect transistor (FBFET) for circuit simulations by fitting the model to measurement results. We fabricated a FBFET and investigated the DC and transient characteristics. The fabricated FBFET has an extremely low sub-threshold slope and a low off current. The FBFET operates as a forward-biased PN diode after the device is turned on due to the positive feedback loop between the integrated charges and the potential barrier. When enough electrons are accumulated in the floating body, the potential barrier is lowered and the FBFET is turned on rapidly, and due to the integrated charges, the FBFET has memory characteristics which approximate hose of 1T-DRAM. Reflecting these electrical characteristics of the FBFET, we undertook SPICE modeling and obtained simulation results that were similar to the measurement characteristics. Finally, we implement a modified inverter with the FBFET connected in parallel with an n-type MOSFET (NMOS). Due to the superior sub-threshold characteristics of the FBFET, it effectively suppresses the sub-threshold currents.

Modeling of Multi-State Si and Ge Cladded Quantum Dot Gate FETs Using Verilog and ABM Simulations

Quantum dot gate (QDG) field-effect transistors (FETs) fabricated using Si and Ge quantum dot layers, self-assembled in the gate region over the tunnel oxide, have exhibited 3- and 4-state behavior applicable for ternary and quaternary logic, respectively. This paper presents simulation of QDG-FETs comprising mixed Ge and Si quantum dot layers over tunnel oxide using an analog behavior model (ABM) and Verilog model. The simulations reproduce the experimental I-V characteristics of a fabricated mixed dot QDG-FET. GeOx-cladded Ge quantum dot layer is in interface to the tunnel oxide and is deposited over with a SiOx-cladded Si quantum dot layer. The fabricated QDG-FET has one source and one gate. The ABM simulation models QDG-FET using conventional BSIM 3V3 FETs with capacitances and other device parameters. In addition, VERILOG model is presented. The agreement in circuit and quantum simulations and experimental data will further advance in the designing of QDG-FET-based analog-to-digital converters (ADCs), 2-bit logic gates and SRAM cells.

Ultrathin Junctionless Nanowire FET Model, Including 2-D Quantum Confinements

In this paper, we develop an explicit model to predict the dc electrical behavior in ultrathin surrounding gate junctionless (JL) nanowire field-effect transistors (FETs). The proposed model considers 2-D electrical and geometrical confinements of carrier charge density within few discrete subbands. Combining a parabolic approximation of the Poisson equation, the first-order perturbation theory for the Schrodinger subband energy eigen-values and the Fermi–Dirac statistics for the confined carrier density lead to an explicit solution of the dc characteristic in ultrathin JL devices. Validity of the model has been verified with technology computer-aided design simulations. The results confirm its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. This represents an essential step toward analysis of circuits based on JL nanowire devices.

Nanowire reconfigurable FET as biosensor: Based on dielectric modulation approach

In this paper, we have developed analytical surface potential and threshold voltage model of nanowire reconfigurable Field Effect Transistor (FET) which acts as a biosensor to detect the biomolecules, based on dielectric modulation approach. Due to its reconfigurable behavior, it acts as both p-type and n-type depending on the polarity of the biasing and hence find wide spread applications in the field of Programmable Logic Arrays (PLAs). The same is employed here as a bio sensor device with split gates and a cavity for biomolecules immobilization on a thin layer of silicon dioxide as adhesive layer. When the biosensor interacts with the bio targets of the cavity, the electrostatic properties of the device including variation in potential profile and threshold voltage shift get affected and thus have been identified as detection metric in this present work. The characteristic trends of the biosensor are studied with varying height, dielectric constant and charge of the bio-species as polarity of the applied biases change. In addition to this, sensitivity of nanowire RFET is analyzed by assessing the threshold voltage variation which is further compared with equivalent MOSFET biosensor. All the analytical results obtained are corroborated with technology computer-aided-design (TCAD) simulation data to verify the precision of our model.

A review on the artificial neural network applications for small‐signal modeling of microwave FETs

AbstractThe purpose of this paper is to provide a comprehensive overview of the field‐effect transistor (FET) small‐signal modeling using artificial neural networks (ANNs). To gain an in‐depth insight into how to effectively develop an ANN model, we present a comparative study on the application of the ANNs for modeling the scattering (S‐) parameters of a variety of FET technologies versus bias point, ambient temperature, and geometrical dimensions. As will be shown, the main challenge consists of identifying the most appropriate ANN model for the specific case under study. This is because the performance of an ANN‐based model can vary significantly, depending especially on the choice of the model structure and the size and parameters of the chosen ANN. In addition, the choice of the model is related directly to the behavior of the FET characteristics, which might greatly depend on the selected device technology and operating conditions. The analysis of the present comparative study allows understanding how to properly construct ANN models to perform at their best for a successful FET modeling.

Performance enhancement of triple material double gate TFET with heterojunction and heterodielectric

In this paper, we proposed a 2 dimensional model of tripple material double gate Tunnel Field Effect Transistor (TM-DG TFET) with hetero-junction formed by germanium and silicon materials in the source-channel junction and heterodielectric gate stack is used with Silicon Dioxide (SiO2) and Hafnium Dioxide (HfO2) as dielectric materials. The electrical characteristics like surface potential, electric field, drain current and transconductance are demonstrated for the device by using commercially available 2D numerical device simulator Silvaco TCAD ATLAS. The variation of the drain currnet or ON current with the varying channel length (L), doping concentration of drain and source (NA and ND), thickness of device (tsi) and effective oxide layer thickness (tox) of the device is evaluated and presented. It is demonstrated that the proposed TM-DG TFET structure has better performance than single material and double material TFET. The proposed model shows a lower ambipolar current and a better ION/IOFF ratio. Moreover, the influence of Germanium/Silicon hetero-junction has reduces the tunneling barrier width is exactly depicted. Hence the ON current (10−3A) of the proposed device is improved at the level of CMOS transistors.

Empirical Drain Current Model of Graphene Field-Effect Transistor for Application as a Circuit Simulation Tool

In this paper, an empirical model of dual gate graphene field-effect transistor (GFET) has been developed. The explicit form of drain current expression has been established analytically based on a drift-diffusion approach. The channel sheet charge density helps us to determine the quantum capacitance more accurately. The channel potential has been derived from the equivalent circuit. The improvement of carrier mobility has been included. The closed form expression is obtained with a few fitting parameters to explore the model characteristics. The model is also valid for single gate technology. The model has been verified against some pioneering experimental results reported in literatures. Model simulation agrees well with existing experimental data. We have also compared the results of the model obtained from NANOHUB online simulator for further verification. The characteristics of small signal parameters of this GFET model have been observed and cut-off frequency has been determined. The developed analytical GFET model is also found to be computationally efficient. It is observed that with ± 10% variation in top gate oxide thickness, maximum drain current and peak transconductance vary by (−11.53%/ + 14%) and (−25%/+31.25%), respectively. The double gate bilayer GFET model is implemented in Verilog-A and verified for a voltage amplifier in SPICE environment.

A New Surface Potential and Drain Current Model of Dual Material Gate Short Channel Metal Oxide Semiconductor Field Effect Transistor in Sub-Threshold Regime: Application to High-k Material HfO2

A New Surface Potential and Drain Current Model of Dual Material Gate Short Channel Metal Oxide Semiconductor Field Effect Transistor in Sub-Threshold Regime: Application to High-k Material HfO₂

An Angelov Large-Signal FET Model Up To 67 GHz

A modified Angelov large-signal field effect transistor model is proposed in which dispersion branches are neglected. A systematic procedure is built up to directly extract all the key model parameters from hybrid measurements including dc and RF characteristics. Source-pull and load-pull iterations are conducted to verify the accuracy of large-signal performances. Owing to the effective parameter extraction and RF de-embedding, the modeled results show an excellent agreement with the measured ${I}$ – ${V}$ relations and multi-bias S-parameters up to 67 GHz. Output power and power added efficiency are sufficiently validated at 30 GHz.

A computationally efficient hybrid approach based on artificial neural networks and the wavelet transform for quantum simulations of graphene nanoribbon FETs

Numerical modeling of graphene nanoribbon field-effect transistors (GNRFETs) using quantum-mechanical approaches is often associated with a heavy computational burden, indicating the urgent need for new methods to resolve this issue. A computationally efficient hybrid approach for quantum simulations of ballistic GNRFETs is developed herein. The proposed simulation method is based on solving the two-dimensional (2D) Poisson equation using both wavelet-based adaptive meshing and wavelet-based matrix compression techniques, self-consistently, with well-trained neural network models that imitate the mode-space (MS) nonequilibrium Green’s function (NEGF) solver in generating the charge density. The results obtained by applying the hybrid approach show good agreement with NEGF simulations. Numerical experiments reveal that the developed simulation method can offer a speed-up of about one order of magnitude over the conventional MS NEGF approach. The encouraging results obtained in this work indicate that the developed numerical model is particularly appropriate for incorporation into nanoelectronic device simulators to investigate future GNRFET-based circuits.

Boltzmann transport equation‐based semi‐classical drain current model for bilayer GFET including scattering effects

In this study, a drain current model of bilayer graphene field-effect transistor (GFET) has been developed. The Boltzmann transport approach is considered to develop this model including the scattering effects. The effects of optical phonon scattering, acoustic phonon scattering and carrier-carrier scattering have been included. The effective voltages at top and back gates induce net mobile sheet charge density in graphene channel. Mobile sheet charge density helps to determine the quantum capacitance. Channel potential is derived from equivalent circuit. The electronic transport phenomena of carriers in channel are explained for the contribution of both electron and hole charge density. Finally, the expression of drain current is determined using the Boltzmann transport equation under non-equilibrium condition. Contact resistances at source and drain regions are considered to determine the accurate drain current. The small signal parameters of GFET are determined from drain current and net charge density, and finally using these parameters the authors have calculated the cut-off frequency of the model. We validate the model with several contemporary experimental results. Utilising the model, we have also explored the impact of back-gate bias, top-gate bias and channel length on the device characteristics.

A fuzzy Anti-lock braking system (ABS) controller using CMOS circuits

In this paper, an Anti-lock braking system (ABS) is designed using a fuzzy logic controller (FLC). The FLC is designed in 0.35 μm standard CMOS process and this design of the circuit makes it having high speed and low power consumption. Also, all the controlling signals and input signals are in voltage form and there is no need for digital programming. Voltage mode design of the circuits leads to the convenient use of FLC with sensors. The objective function is designed to keep the wheel slip to a desired level so that maximum wheel tractive force and maximum vehicle deceleration are achieved. By training this function to the Adaptive Nero-Fuzzy Inference System (ANFIS) of MATLAB software the main parameters of fuzzy controller singletons and shape of Membership Function Generators (MFGs) are measured, then all the circuits of the proposed fuzzy logic controller is designed using Complementary Metal-Oxide-Semiconductor (CMOS) circuits, at the end simulation results of the fuzzy logic controller using Hspice simulator and BSIM3v3 (Berkeley Short-Channel Insulated gate field effect transistor Model) parameters verifies the performance and functionality of the design.