Μm Gate Length Research Articles

Static characteristics and short channel effect in enhancement-mode AlN/GaN/AlN N-polar MISFET with self-aligned source/drain regions

This paper aims to simulate the I–V static characteristic of the enhancement-mode (E-mode) N-polar GaN metal—insulator—semiconductor field effect transistor (MISFET) with self-aligned source/drain regions. Firstly, with SILVACO TCAD device simulation, the drain—source current as a function of the gate—source voltage is calculated and the dependence of the drain—source current on the drain—source voltage in the case of different gate—source voltages for the device with a 0.62 μm gate length is investigated. Secondly, a comparison is made with the experimental report. Lastly, the transfer characteristic with different gate lengths and different buffer layers has been performed. The results show that the simulation is in accord with the experiment at the gate length of 0.62 μm and the short channel effect becomes pronounced as gate length decreases. The E-mode will not be held below a 100 nm gate length unless both transversal scaling and vertical scaling are being carried out simultaneously.

Demonstration of radio-frequency response of amorphous IGZO thin film transistors on the glass substrate

The relatively high-mobility metal-oxide thin-film transistors (TFTs) have the potential to realize radio-frequency (RF) circuits operating in the megahertz regime. Here, we investigate the RF performance of amorphous indium gallium zinc oxide (a-IGZO) TFTs on the glass substrate with the sputtered channel layer. The device exhibits a high current density of 22.6mA/mm by employing thin bi-layer Al2O3/SiO2 gate dielectrics. The 1.5μm gate length device achieves a current gain cutoff frequency fT of 384MHz and a maximum frequency of oscillation fmax of 1.06GHz. The record high RF response among the amorphous oxide channels makes it possible to explore new large-area electronics applications, such as low-cost radio frequency identification (RFID) tags. Furthermore, the corresponding small signal parameters were extracted and the voltage dependences of RF response were studied.

Design and simulation of a novel 1400 V–4000 V enhancement mode buried gate GaN HEMT for power applications

A novel enhancement mode structure, a buried gate gallium nitride (GaN) high electron mobility transistor (HEMT) with a breakdown voltage (BV) of 1400 V–4000 V for a source-to-drain spacing (LSD) of 6 μm–32 μm, is investigated using simulations by Silvaco Atlas. The simulations are based on meticulous calibration of a conventional lateral 1 μm gate length GaN HEMT with a source-to-drain spacing of 6 μm against its experimental transfer characteristics and BV. The specific on-resistance RS for the new power transistor with the source-to-drain spacing of 6 μm showing BV = 1400 V and the source-to-drain spacing of 8 μm showing BV = 1800 V is found to be 2.3 mΩ · cm2 and 3.5 mΩ · cm2, respectively. Further improvement up to BV = 4000 V can be achieved by increasing the source-to-drain spacing to 32 μm with the specific on-resistance of RS = 35.5 mΩ · cm2. The leakage current in the proposed devices stays in the range of ∼5 × 10−9 mA mm−1.

Electron density and currents of AlN/GaN high electron mobility transistors with thin GaN/AlN buffer layer

AlN/GaN high electron mobility transistor (HEMT) structures with thin GaN/AlN buffer layer have been analyzed theoretically and experimentally, and the effects of the AlN barrier and GaN buffer layer thicknesses on two-dimensional electron gas (2DEG) density and transport properties have been evaluated. HEMT structures consisting of [300 nm GaN/ 200 nm AlN] buffer layer on sapphire were grown by plasma-assisted molecular beam epitaxy and exhibited a remarkable agreement with the theoretical calculations, suggesting a negligible influence of the crystalline defects that increase near the heteroepitaxial interface. The 2DEG density varied from 6.8 × 1012 to 2.1 × 1013 cm−2 as the AlN barrier thickness increased from 2.2 to 4.5 nm, while a 4.5 nm AlN barrier would result to 3.1 × 1013 cm−2 on a GaN buffer layer. The 3.0 nm AlN barrier structure exhibited the highest 2DEG mobility of 900 cm2/Vs for a density of 1.3 × 1013 cm−2. The results were also confirmed by the performance of 1 μm gate-length transistors. The scaling of AlN barrier thickness from 1.5 nm to 4.5 nm could modify the drain-source saturation current, for zero gate-source voltage, from zero (normally off condition) to 0.63 A/mm. The maximum drain-source current was 1.1 A/mm for AlN barrier thickness of 3.0 nm and 3.7 nm, and the maximum extrinsic transconductance was 320 mS/mm for 3.0 nm AlN barrier.

Compact modelling of InAlN/GaN HEMT for low noise applications

This paper presents results of high-frequency noise modelling of InAlN/GaN high electron mobility transistors (HEMTs) with different formulations of the minimum noise figure NFmin. Current–voltage characteristics and s-parameters of 0.15 μm gate length and 2 × 75 μm gate width InAlN/GaN HEMTs were measured at room temperature in a wide frequency range (300 MHz to 50 GHz) and bias range (VGS from −4.8 to 1 V and VDS from 0 to 21 V). Both the EEHEMT1 and Angelov GaN compact models yielded excellent agreement for transfer and output characteristics, transconductance gm, and fT, fmax. High-frequency noise parameters NFmin, Rn, ΓOPT of InAlN/GaN HEMT were measured in 8–50 GHz frequency band. Noise formulation within the EEHEMT1 model underestimates the measured NFmin and Rn. The well known three-parameter PRC noise model is in a better agreement with the measured data but neglects the shot noise resulting from the gate leakage. The inductive degenerated source matching method and EEHEMT1 were used to design a single stage LNA operated at 8 GHz frequency. A 10 dB gain with an input reflection of −12 dB with a 2.5 dB of noise factor were obtained at 8 GHz.

Fabrication and Performance of InAlN/GaN-on-Si MOSHEMTs with LaAlO3 Gate Dielectric Using Gate-First CMOS Compatible Process at Low Thermal Budget

Introduction Recently, lattice matched InAlN/AlN/GaN-on-silicon integration approach has attracted increasing attention due to the availability of high-quality GaN epiwafers with high throughput epitaxial growth on large area Si substrates for applications in power and RF devices with low power consumption [1-2]. Meanwhile, the development of gate-first process is useful to realize future self-aligned transistor structures. Conventional fabrication of InAlN/GaN high electron mobility transistors (HEMTs) or metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) involves gate-last process where high temperature (>800 oC) annealing is required to form Ti/Al/Ni/Au source and drain ohmic contacts [3]. This is a consequence of traditional gate metallization (e.g., Ni/Au) and gate dielectric not being able to survive such a high ohmic annealing temperature. Therefore, the development of good ohmic contacts with a low thermal annealing budget and thermally stable gate dielectric is required to realize the gate-first process integration for InAlN/GaN HEMTs/MOSHEMTs. In the present work, we report the fabrication and characterization of InAlN/GaN MOSHEMTs using a lift-off free, gate-first CMOS compatible process developed at low thermal budget. Experiment The lattice-matched In0.18Al0.82N/AlN/GaN-on-Si (111) HEMT structure used in this experiment is shown schematically in Fig. 1. The MOSHEMT fabrication using a gate-first process started from mesa isolation followed by 20 nm thick LaAlO3 (LAO) deposition using pulsed laser deposition (PLD) with a substrate temperature of 300 oC. Then, W was sputter deposited followed by gate definition using photolithography and dry etching method. Thereafter, Hf/Al/Ta layer was sputter deposited followed by rapid thermal annealing at 600 oC for 60 s in vacuum to form source and drain ohmic contacts. Results and Discussion The contact resistance and contact resistivity of Hf/Al/Ta ohmic contacts, as analyzed from linear transmission line method (LTLM), are found to ~0.60 Ω·mm and 6.7x10-6 Ω·cm2, respectively. At first, the thermal stability and reliability of the LAO gate dielectric upon 600 oC ohmic anneal in vacuum was optimized under several oxygen partial pressures during PLD. Comparison of capacitance-voltage and reverse gate leakage current characteristics of fabricated devices subject to different oxygen partial pressures in the range from 3.1×10-5 Torr to 5×10-3 Torr are shown in Figs. 2(a) and 2(b), respectively. It is found that LAO deposited under an oxygen partial pressure of 2.7×10-4 Torr exhibits the lowest gate leakage and highest accumulation capacitance, predominantly arisen by an increased dielectric permittivity (k~23.2). Finally, the gate-first CMOS compatible MOSHEMTs were fabricated by choosing the above optimized deposition condition for PLD (2.7×10-4 Torr @ 300 oC) of LAO. Devices having gate dimensions of W/L = 2×50/1 μm, gate-to-source distance of Lgs ~ 2 μm, gate-to-drain distance of Lgd ~ 6 μm, were used for DC output and transfer characterizations. The DC output and transfer characteristics are shown in Figs. 3 (a) and (b), respectively. The MOSHEMTs achieve a saturation drain current (Idsat) of 500 mA/mm at zero gate voltage, threshold voltage (Vth) of -12.6 V, maximum extrinsic transconductance (Gmax) of 44 mS/mm and on-resistance (Ron) of ~ 14 Ω/mm. Conclusion In conclusion, a gate-first CMOS compatible process for InAlN/AlN/GaN-on-Si MOSHEMTs fabrication has been developed. A low thermal budget (600 oC) for ohmic annealing is achieved through the use of Hf/Al/Ta source-drain contacts, thus allowing the fabrication of gate-first CMOS compatible MOSHEMTs using LaAlO3 as the gate dielectric as well as for device passivation purpose. The reasonable DC performance demonstrated (Idsat = 500 mA/mm, Gmax = 44 mS/mm, etc.) for a 1 μm gate length shows promising possibility for gate-first process integration of InAlN/GaN-on-Si MOSHEMTs.

Fabrication and Performance of InAlN/GaN-on-Si MOSHEMTs with LaAlO3 Gate Dielectric Using Gate-First CMOS Compatible Process at Low Thermal Budget

A gate-first CMOS compatible process at low thermal budget to fabricate InAlN/GaN-on-Si MOSHEMTs is reported. This is made possible by a good quality LaAlO3 gate dielectric (k ~ 21.8) and Hf/Al/Ta ohmic contacts that require low annealing temperature. The reverse leakage current of the W/LaAlO3 gate stack remains low (< 3´10-7 mA/mm at -10 V) upon ohmic contact annealing at 600 oC. The fabricated LaAlO3 gate dielectric MOSHEMTs demonstrate a reasonable DC performance (Idsat ~ 510 mA/mm, Gmax ~ 44 mS/mm) for a 1 μm gate length device.

Fabrication and Analysis of a ${\rm Si}/{\rm Si}_{0.55}{\rm Ge}_{0.45}$ Heterojunction Line Tunnel FET

This paper presents a new integration scheme to fabricate a Si/Si0.55Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1- μm gate length device shows on current in excess of 20 μA/μm at VGS=VDS=1.2 V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by ~ 0.35 V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration.

Design of Ultra-Low Phase Noise and High Power Integrated Oscillator in $0.25~\mu{\rm m}$ GaN-on-SiC HEMT Technology

A novel ultra-low phase noise and high power integrated oscillator is presented in this letter. The proposed oscillator, based on GaN-on-SiC high electron mobility transistor (HEMT) with 0.25 μm gate length and 800 μm gate width, delivers 21 dBm output power when biased at VGS=-3 V and VDD = 28 V. Phase noise was measured to be -112 dBc/Hz at 100 kHz offset and -135 dBc/Hz at 1 MHz offset from 7.9 GHz carrier, respectively. To the best of our knowledge, it achieves the lowest phase noise compared to other GaN HEMT based integrated oscillators. It is also comparable in performance to the state-of-the-art ultra-low phase noise oscillators designed in InGaP technology, while delivering more than 10 times higher output power. In addition, this oscillator also exhibits a minimum second harmonic suppression of 28.65 dBc and more than 60 dBc third harmonic suppression. The chip size is 1.1×0.6 mm2. The results show that the proposed oscillator has the potential to be used for both low phase noise and high power microwave source applications.

Thermally stable In0.7Ga0.3As/In0.52Al0.48As pHEMTs using thermally evaporated palladium gate metallization

This work described the fabrication and performances of strained channel In0.52Al0.47As/In0.7Ga0.3As/InP pHEMTs with thermally evaporated Pd/Ti/Au gate metallization. The electrical characteristics of these Pd-gate devices are studied to investigate the effects of changing the Pd metal thickness, annealing temperature and annealing time. Following annealing at 200 °C for 35 min, a 10 nm Pd-gate device displays a VTH of −0.25 V, which is significantly smaller compared to those with Ti/Au gate schemes showing VTH = −0.75 V. A 1 um gate length device exhibits an improved Gm of 580 mS mm−1 (from 500 mS mm−1), a high IDSmax of 400 mA mm−1 (from 330 mA mm−1) and good fT and fmax of 24.5 and 49 GHz commensurate with the 1 µm gate length. All these enhancements are attributed to the controllable gate sinking of Pd. The device shows no significant degradation even after annealing at 230 °C for more than 5 h, which implies that the reliability of these Pd-gate structures is excellent.

Drift-diffusion and hydrodynamic modeling of current collapse in GaN HEMTs for RF power application

Current collapse due to the trapping/de-trapping of the carriers at the surface and in the bulk of a 0.25 µm gate length AlGaN/GaN high electron mobility transistor is investigated using 2d technology computer aided design transient simulations. Gate and drain pulse techniques are used to study the dynamic picture of trapping and de-trapping of carriers within drift-diffusion and hydrodynamic transport models. In addition, coupled electrical and thermal simulations are performed to model the energy exchange of the carriers with the lattice and to predict electron temperature in the channel. It is found that current degradation upon electrical stress is due to two different types of traps, donor-like traps and acceptor-like traps, respectively. The collapse next to 5% and 75% was observed for bulk and surface traps, respectively. The combined effect of surface and bulk traps on current transient characteristics has been investigated and simulations are in very good qualitative agreement with the experimental observations.

Microwave noise characterization of graphene field effect transistors

The microwave noise parameters of graphene field effect transistors (GFETs) fabricated using chemical vapor deposition graphene with 1 μm gate length in the 2 to 8 GHz range are reported. The obtained minimum noise temperature (Tmin) is 210 to 610 K for the extrinsic device and 100 to 500 K for the intrinsic GFET after de-embedding the parasitic noise contribution. The GFET noise properties are discussed in relation to FET noise models and the channel carrier transport. Comparison shows that GFETs can reach similar noise levels as contemporary Si CMOS technology provided a successful gate length scaling is performed.

High-performance self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors by in-situ atomic-layer-deposited HfO2

Self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors (MOSFETs) have been fabricated using the gate dielectrics of in-situ directly atomic-layer-deposited (ALD) HfO2 followed by ALD-Al2O3. There were no surface pretreatments and no interfacial passivation/barrier layers prior to the ALD. TiN/Al2O3 (4 nm)/HfO2 (1 nm)/In0.53Ga0.47As/InP MOS capacitors exhibited well-behaved capacitance-voltage characteristics with true inversion behavior, low leakage current densities of ∼10−8 A/cm2 at ±1 MV/cm, and thermodynamic stability at high temperatures. Al2O3 (3 nm)/HfO2 (1 nm)/In0.53Ga0.47As MOSFETs of 1 μm gate length, with 700 °C–800 °C rapid thermal annealing in source/drain activation, have exhibited high extrinsic drain current (ID) of 1.5 mA/μm, transconductance (Gm) of 0.84 mS/μm, ION/IOFF of ∼104, low sub-threshold swing of 103 mV/decade, and field-effect electron mobility of 1100 cm2/V · s. The devices have also achieved very high intrinsic ID and Gm of 2 mA/μm and 1.2 mS/μm, respectively.

Low ohmic contact AlN/GaN HEMTs grown by MOCVD

AlN/GaN high-electron-mobility transistors (HEMTs) on SiC substrates were fabricated by metal-organic chemical vapor deposition (MOCVD) and then characterized. An Si/Ti/Al/Ni/Au stack was used to reduce ohmic contact resistance (0.33 Ω·mm) at a low annealing temperature. The fabricated devices exhibited a maximum drain current density of 1.07 A/mm (VGS = 1 V) and a maximum peak extrinsic transconductance of 340 mS/mm. The off-state breakdown voltage of the device was 64 V with a gate—drain distance of 1.9 μm. The current gain extrinsic cutoff frequency fT and the maximum oscillation frequency fmax were 36 and 80 GHz with a 0.25 μm gate length, respectively.

Degradation in AlGaN/GaN heterojunction field effect transistors upon electrical stress: Effects of field and temperature

AlGaN/GaN heterojunction field effect transistors (HFETs) with 2 μm gate length were subjected to on-state-high-field (high drain bias and drain current) and reverse-gate-bias (no drain current and reverse gate bias) stress at room and elevated temperatures for up to 10 h. The resulting degradation of the HFETs was studied by direct current and uniquely phase noise before and after stress. A series of drain and gate voltages was applied during the on-state-high-field and reverse-gate-bias stress conditions, respectively, to examine the effect of electric field on degradation of the HFET devices passivated with SiNx. The degradation behaviors under these two types of stress conditions were analyzed and compared. In order to isolate the effect of self-heating/temperature on device degradation, stress experiments were conducted at base plate temperatures up to 150 °C. It was found that the electric field induced by reverse-gate-bias mainly generated trap(s), most likely in the AlGaN barrier, which initially were manifested as generation-recombination (G-R) peak(s) in the phase noise spectra near 103 Hz. Meanwhile electric field induced by on-state-high-field stress mainly generated hot-electron and hot-phonon effects, which result in a nearly frequency independent increase of noise spectra. The external base plate temperatures promote trap generation as evidenced by increased G-R peak intensities.

AlGaN/GaN HEMTs on diamond substrate with over 7 W/mm output power density at 10 GHz

Record RF performance of AlGaN/GaN high electron mobility transistors (HEMTs) on a diamond substrate with over 7 W/mm output power density at 10 GHz is reported. It is achieved along with the peak power-added-efficiency over 46% and power gain over 11 dB for 2 × 100 µm gate-width HEMTs at 40 V drain bias. Device wafers are prepared by first removing the host Si (111) substrate and nitride transition layers beneath the channel, depositing a 50 nm dielectric onto the exposed GaN buffer, and finally growing 100 µm of a chemical vapour deposition diamond onto the dielectric adhering to the epitaxial AlGaN/GaN. This approach enables the active GaN channel to be brought within 1 µm of the diamond substrate. Test HEMTs are fabricated using a dielectrically defined 0.25 µm gate length process.

Simulation of an AlGaN/GaN HEMT for Ka-Band

A physical model of 0.24μm gate-length and 50μm gate-width AlGaN/GaN HEMTs is designed in the paper including lateral structure and longitudinal material parameters. Then DC and high frequency characteristics are both simulated and analyzed. The results show that the saturation drain current is 0.8A/mm at zero bias and the maximum transconductance is 350mS/mm. The current gain cutoff frequency (fT) and maximum frequency of oscillation (fmax) are 35GHz and 107GHz respectively at -2V gate voltage and 25V drain voltage. The maximum available power gains (MAG) is 10.2dB at 40GHz. Therefore, the structure can be applied to Ka-band.

Device characteristics of InAlSb/InAs and InAlSb/InAsSb HFETs

The successful fabrication of InAlSb/InAs and InAlSb/InAsSb HFETs using recessed gate technology is reported. Epitaxial growth, device fabrication and characterisation are discussed in this Letter. A comparison of the two kinds of HFETs shows that the use of Sb in the InAs channel layer can effectively reduce the gate leakage resulting from the band-to-band tunnelling. This improvement is primarily because of increased separation between the conduction band edge of the InAsSb channel layer and the valence band edge of the InAlSb top barrier layer. An InAlSb/InAsSb HFET with 2 μm gate length and 50 μm gate width shows ID = 596 mA/mm and gm = 1 S/mm.

High Breakdown Voltage GaN HEMT Device Fabricated on Self-Standing GaN Substrate

In this letter, a high breakdown voltage GaN HEMT device fabricated on semi-insulating self-standing GaN substrate is presented. High quality AlGaN/GaN epilayer was grown on self-standing GaN substrate by metal organic chemical vapor deposition. A 0.8μm gate length GaN HEMT device was fabricated with oxygen plasma treatment. By using oxygen plasma treatment, gate forward working voltage is increased, and a breakdown voltage of more than 170V is demonstrated. The measured maximum drain current of the device is larger than 700 mA/mm at 4V gate bias voltage. The maximum transconductance of the device is 162 mS/mm. In addition, high frequency performance of the GaN HEMT device is also obtained. The current gain cutoff frequency and power gain cutoff frequency are 19.7 GHz and 32.8 GHz, respectively. A high fT-LG product of 15.76 GHzμm indicating that homoepitaxy technology is helpful to improve the frequency performance of the device.

Electron transport in passivated AlGaN/GaN/Si HEMTs

AlGaN/GaN/Si high electron mobility transistors (HEMTs) grown by molecular beam epitaxy are investigated using direct-current and radio-frequency measurements. As has been found, the maximum of drain current achieves 881mA/mm with an extrinsic current gain cutoff frequency of 37GHz for a 0.25µm gate length. Pulsed characteristics also showed a reduction of trapping centers that improves the quality of the epilayers.