Μm Complementary Metal Oxide Semiconductor Research Articles

High‐order realisation of MOSFET‐only band‐pass filters for RF applications

The authors present two new metal oxide semiconductor field effect transistor (MOSFET)-only second-order voltage and transadmittance-mode band-pass filters (BPFs) employing only five transistors without using any passive elements such as a resistor, a capacitor, and an inductor. As a result, both proposed circuits possess low-power consumption and occupy small chip area. The first proposed filter enjoys low output impedance and offset cancellation for voltage-mode operation while the second proposed filter has low supply voltage. The centre frequency of both proposed filters can be electronically tuned by varying biasing voltage. To demonstrate the performance of the proposed filters, effects of output transconductance of transistors have been investigated and equations of input referred noise have been obtained. Furthermore, fourth-order voltage and transadmittance-mode BPF which is derived the first proposed filter is presented and its simulation results are given. All proposed filters are laid-out in the Cadence environment using Taiwan semiconductor manufacturing company (TSMC) 0.18 µm complementary metal oxide semiconductor (CMOS) technology parameters. The required chip area of the fourth-order voltage and transadmittance-mode band-pass filter is 1100 μm2 and the power consumption is about 436 µW.

A Low Phase-noise 0.9/1.8 ㎓ Dual-band LC VCO using 0.18 ㎛ CMOS Technology

This paper presents a low phase–noise 0.9/1.8 ㎓ dual-band LC voltage controlled oscillator (VCO) using 0.18 ㎛ complementary metal-oxide semiconductor (CMOS) technology. The proposed CMOS-based LC VCO is composed of varactor diodes and a switched capacitor array for coarse and fine tuning, and a switched differential inductor, which controls the dual-band operation. The CMOS-based LC VCO is also implemented with low phase–noise performance using two series inductors in common source nodes. The proposed CMOS-based LC VCO provides dual bands of 0.9 ㎓ and 1.8 ㎓, and phase noise of -135 ㏈c/㎐ and -126 ㏈c/㎐, respectively, at a 1 ㎒ offset. The chip size is 1.3 ㎜ × 1.4 ㎜, including pads. The DC power consumption is 16.2 ㎽ at a 1.8 V supply voltage.

Design and analysis of CMOS RCG transimpedance amplifier based on elliptic filter approach

This study presents a new design of compact transimpedance amplifier (TIA) for optical communication applications. By adopting the regulated common gate (RCG) topology, the proposed amplifier is designed and synthesised based on a third-order elliptic filter approach. Implemented in 0.13 μm complementary metal oxide semiconductor technology, the post layout simulation results provide 50 dB Ω of direct current gain, 15 GHz of bandwidth, 20 pA/√Hz as an input referred noise current performance. The proposed RCG TIA occupies a 19 × 36 μm 2 while consuming 5.34 mW under 1.2 V supply voltage, only.

Integrated Optoelectronic Position Sensor for Scanning Micromirrors.

Scanning micromirrors have been used in a wide range of areas, but many of them do not have position sensing built in, which significantly limits their application space. This paper reports an integrated optoelectronic position sensor (iOE-PS) that can measure the linear displacement and tilting angle of electrothermal MEMS (Micro-electromechanical Systems) scanning mirrors. The iOE-PS integrates a laser diode and its driving circuits, a quadrant photo-detector (QPD) and its readout circuits, and a band-gap reference all on a single chip, and it has been fabricated in a standard 0.5 μm CMOS (Complementary Metal Oxide Semiconductor) process. The footprint of the iOE-PS chip is 5 mm × 5 mm. Each quadrant of the QPD has a photosensitive area of 500 µm × 500 µm and the spacing between adjacent quadrants is 500 μm. The iOE-PS chip is simply packaged underneath of an electrothermally-actuated MEMS mirror. Experimental results show that the iOE-PS has a linear response when the MEMS mirror plate moves vertically between 2.0 mm and 3.0 mm over the iOE-PS chip or scans from −5 to +5°. Such MEMS scanning mirrors integrated with the iOE-PS can greatly reduce the complexity and cost of the MEMS mirrors-enabled modules and systems.

Low‐power sample and hold circuits using current conveyor analogue switches

This study presents low-power sample and hold (S/H) circuits using second-generation current conveyor (CCII). Unlike previous S/H circuits, switch of the proposed S/H circuits can be obtained using CCII which works as current conveyor analogue switch (CCAS). The state of CCAS is controlled by sampling pulse that can be applied via its bias current source. The proposed S/H circuits offer low-power consumption, high-speed and absent from non-overlapping clock signal requirements. Three configurations of S/H circuit are proposed, namely single-ended S/H, differential S/H and serial-to-parallel S/H circuits. The proposed S/H circuits have been simulated using 0.18 μm complementary metal oxide semiconductor (CMOS) process from Taiwan semiconductor manufacturing company (TSMC). The simulation results are used to confirm the workability of the proposed structures.

Analytical design technique for real‐to‐real single‐ and dual‐frequency impedance matching networks in lossy passive environment

A passive-loss accounted analytic design technique for impedance matching networks is proposed here for efficient radio frequency (RF) circuit design. The impact of component losses on matching performance is briefed initially. To overcome the matching impact due to component losses, a set of modified equations are introduced which finds the accurate inductor and capacitor values accounting component losses. The proposed technique is applied for single-frequency L-match, Pi-match, Tmatch and dual-frequency L-match networks. The improvement in matching performance by using the proposed design technique is validated through simulations and measurements in UMC 0.18 μm complementary metal oxide semiconductor technology. The measurement results closely (90-95%) follow ideal component performance. Hence, the proposed passive-loss accounted design technique will be more useful in accurate low power RF circuit design.

Fully integrated CMOS power amplifier using resistive current combining technique

This study presents a fully integrated complementary metal oxide semiconductor (CMOS) power amplifier (PA) covering LTE-advanced bands from 825 to 915 MHz for cellular application and the bands of 978 MHz universal access transceiver mode and 1090 MHz extended squitter mode of an automatic dependent surveillance-broadcast transmitter for the unmanned aircraft system. The 3.63 mm × 0.95 mm PA including all on-chip input and output matching networks, fabricated using the 0.18 μm CMOS process exhibits peak output power of 24 dBm, modulated output power of >22 dBm at 978 MHz, the maximum power gain of 27 dB and bandwidth of 290 MHz.

Prolonged Corrosion Stability of a Microchip Sensor Implant during In Vivo Exposure.

A microelectronic biosensor was subjected to in vivo exposure by implanting it in the vicinity of m. trapezii (Trapezius muscle) from cattle. The implant is intended for the continuous monitoring of glucose levels, and the study aimed at evaluating the biostability of exposed semiconductor surfaces. The sensor chip was a microelectromechanical system (MEMS) prepared using 0.25 µm complementary metal–oxide–semiconductor CMOS/BiCMOS technology. Sensing is based on the principle of affinity viscometry with a sensoric assay, which is separated by a semipermeable membrane from the tissue. Outer dimensions of the otherwise hermetically sealed biosensor system were 39 × 49 × 16 mm. The test system was implanted into cattle in a subcutaneous position without running it. After 17 months, the device was explanted and analyzed by comparing it with unexposed chips and systems. Investigations focused on the MEMS chip using SEM, TEM, and elemental analysis by EDX mapping. The sensor chip turned out to be uncorroded and no diminishing of the topmost passivation layer could be determined, which contrasts remarkably with previous results on CMOS biosensors. The negligible corrosive attack is understood to be a side effect of the semipermeable membrane separating the assay from the tissue. It is concluded that the separation has enabled a prolonged biostability of the chip, which will be of relevance for biosensor implants in general.

Low‐power successive approximation ADC using split‐monotonic capacitive DAC

A power-efficient successive approximation analogue-to-digital converter (SA-ADC) is proposed. In order to reduce the energy consumption of the employed capacitive digital-to-analogue converter (DAC), a new low-energy capacitor switching technique is proposed which consumes no switching energy during the first three comparison steps. Moreover, an energy-efficient split-monotonic technique is utilised for the rest of the operations. Compared with the capacitor switching technique used in the conventional SA-ADC, the proposed scheme not only reduces the switching energy by 99.23% but also it has lowered the total capacitor size by 75%. Furthermore, in order to realise the proposed capacitor switching scheme, a power-efficient logic circuit is designed which reduces the power consumption of the required control logic circuit by reducing the activity of the employed D-type flip-flops. Based on the proposed scheme, a 10 bit 40 kS/s SA-ADC has been designed and simulated in a 0.18 μm complementary metal-oxide semiconductor technology with a supply voltage of 1 V. Post-layout simulation results show that the proposed ADC circuit achieves a signal-to-noise-and-distortion ratio of 60.8 dB at the cost of 270 nW power consumption, resulting in a figure-of-merit of 7.6 fJ/conversion step.

High-performance programmable grounded resistor and its applications

ABSTRACTProgrammable resistor and analog computational circuits are essential for many applications such as analog signal processing units, automatic gain control, neural, fuzzy and instrumentation systems. A high-performance programmable grounded resistor (PGR) using complementary metal oxide semiconductor (CMOS) technology is proposed in this paper. A highly linear CMOS resistor with equivalent resistance ranging from 9.4 to 1.5 kΩ is obtained by cancelling the non-linear term present in the current equation of an MOSFET working in the linear region. The proposed resistor operates on both positive as well as negative input voltage. The inherited features of PGR are simplicity, extensive control voltage range, wider bandwidth and low-power dissipation. Additionally, analog computational units such as multiplier, squarer and divider are also discussed as applications of the PGR. All circuits are implemented and simulated using TSMC 0.13 µm CMOS technology in SPICE.

COMPARATIVE STUDY OF 0.18ΜM LINEARIZED CMOS LOW NOISE AMPLIFIER

This paper presents a comparative study of linearization techniques for Complementary Metal Oxide Semiconductor low noise amplifier. The study is performed previously reported three different techniques; modified derivative superposition, post distortion and noise/distortion cancellation. To perform the design, cascade amplifier topology and 0.18μm Complementary Metal Oxide Semiconductor process parameters is used. These performance are studied in the frequency range of 1 GHz to 5 GHz through simulation. Simulations are performed in Applied Wave Research design environments program.The results are compared with each other and previously reported publication in ways of Input third order intercept point, Input second order intercept point, gain, input return loss, noise figure and DC power.

RGB LED Driver Circuit Design for an Optical Fiber Sensor System

In this paper, the design of a programmable mixed-signal electronic circuit to control the light output of a red-green-blue (RGB) light emitting diode (LED) to be used in an optical fiber sensor system is presented and discussed. The LED is to be used as a light transmitter (light source) within the sensor system. The output of each LED color is to be independently controlled using either a d.c. current or a pulse width modulation (PWM) encoded current. The idea for, and architecture of, the mixed-signal electronic circuit design is considered as both a discrete implementation using off-the-shelf components and the concept for an application specific integrated circuit (ASIC) solution using a 0.35 µm complementary metal oxide semiconductor (CMOS) fabrication process. In this paper, the design operation principles, circuit architecture, simulation results and hardware requirements for this LED driver circuit are considered.

Novel high PSRR high-order temperature-compensated subthreshold MOS bandgap reference

Novel high power supply rejection ratio (PSRR) high-order temperature-compensated subthreshold metal-oxide-semiconductor (MOS) bandgap reference (BGR) is proposed in Semiconductor Manufacturing International Corporation (SMIC) 0.13 μm complementary MOS (CMOS) process. By adopting subthreshold MOS field-effect transistors (MOSFETs) and the piecewise-curvature temperature-compensated technique, the output reference voltage's temperature performance of the subthreshold MOS BGR is effectively improved. The subthreshold MOS BGR achieves high PSRR performance by adopting the technique of pre-regulator. Simulation results show that the temperature coefficient (TC) of the subthreshold MOS BGR is 1.38×10−6/°C when temperature is changed from −40 °C to 125 °C with a power supply voltage of 1.2 V. The subthreshold MOS BGR achieves the PSRR of −104.54 dB, −104.54 dB, −104.5 dB, −101.82 dB and −79.92 dB at 10 Hz, 100 Hz, 1 kHz, 10 kHz and 100 kHz respectively.

Label-Free Biomedical Imaging Using High-Speed Lock-In Pixel Sensor for Stimulated Raman Scattering.

Raman imaging eliminates the need for staining procedures, providing label-free imaging to study biological samples. Recent developments in stimulated Raman scattering (SRS) have achieved fast acquisition speed and hyperspectral imaging. However, there has been a problem of lack of detectors suitable for MHz modulation rate parallel detection, detecting multiple small SRS signals while eliminating extremely strong offset due to direct laser light. In this paper, we present a complementary metal-oxide semiconductor (CMOS) image sensor using high-speed lock-in pixels for stimulated Raman scattering that is capable of obtaining the difference of Stokes-on and Stokes-off signal at modulation frequency of 20 MHz in the pixel before reading out. The generated small SRS signal is extracted and amplified in a pixel using a high-speed and large area lateral electric field charge modulator (LEFM) employing two-step ion implantation and an in-pixel pair of low-pass filter, a sample and hold circuit and a switched capacitor integrator using a fully differential amplifier. A prototype chip is fabricated using 0.11 μm CMOS image sensor technology process. SRS spectra and images of stearic acid and 3T3-L1 samples are successfully obtained. The outcomes suggest that hyperspectral and multi-focus SRS imaging at video rate is viable after slight modifications to the pixel architecture and the acquisition system.

Low‐voltage fully differential difference transconductance amplifier

A new complementary metal-oxide-semiconductor (CMOS) structure for fully differential difference transconductance amplifier (FDDTA) is presented in this study. Thanks to using the non-conventional quasi-floating-gate (QFG) technique the circuit is capable to work under low-voltage supply of 0.6 V with extended input voltage range and with class AB output stages. The QFG multiple-input metal-oxide-semiconductor transistor is used to reduce the count of the differential pairs that needed to realise the FDDTA with simple CMOS structure. The static power consumption of the proposed FDDTA is 40 μW. The FDDTA was designed in Cadence platform using 0.18 μm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC). As an example of applications a three-stage quadrature oscillator and fifth-order elliptic low-pass filter are presented to confirm the attractive features of the proposed CMOS structure of the FDDTA.

3D integrated monolayer graphene\u2013Si CMOS RF gas sensor platform

Integration of a complementary metal-oxide semiconductor (CMOS) and monolayer graphene is a significant step toward realizing low-cost, low-power, heterogeneous nanoelectronic devices based on two-dimensional materials such as gas sensors capable of enabling future mobile sensor networks for the Internet of Things (IoT). But CMOS and post-CMOS process parameters such as temperature and material limits, and the low-power requirements of untethered sensors in general, pose considerable barriers to heterogeneous integration. We demonstrate the first monolithically integrated CMOS-monolayer graphene gas sensor, with a minimal number of post-CMOS processing steps, to realize a gas sensor platform that combines the superior gas sensitivity of monolayer graphene with the low power consumption and cost advantages of a silicon CMOS platform. Mature 0.18 µm CMOS technology provides the driving circuit for directly integrated graphene chemiresistive junctions in a radio frequency (RF) circuit platform. This work provides important advances in scalable and feasible RF gas sensors specifically, and toward monolithic heterogeneous graphene–CMOS integration generally.

Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier.

We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m2 input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB.

Positive feedback technique and split‐length transistors for DC‐gain enhancement of two‐stage op‐amps

This study presents the design and simulation of a fully differential two‐stage op‐amp in a 0.18 μm complementary metal–oxide–semiconductor process with a 1.8 V supply voltage. In this op‐amp, positive feedback technique and split‐length transistors (SLTs) are employed to increase the DC‐gain of the op‐amp by about 22 dB without affecting the unity‐gain bandwidth (UGBW), stability, power dissipation and output voltage swing of the conventional two‐stage op‐amp. A comprehensive analysis is provided for differential‐mode gain, common‐mode gain, power supply rejection ratio, input‐referred noise, input offset, frequency response and the effect of using SLTs on DC‐gain sensitivity. The proposed op‐amp is utilised in a flip‐around sample‐and‐hold amplifier (SHA). The output spectrum of the SHA shows the total harmonic distortion of 0.0023%. The post‐layout and Monte Carlo simulation results show that the proposed op‐amp has better performance than the state‐of‐the‐art designs.

Design of a new CMOS Low-Power Analogue Neuron

In this paper, a low-power analogue complementary metal oxide semiconductor (CMOS) artificial neuron circuit is presented. The analogue neuron is composed of multiplier and programmable activation function circuits. The proposed four-quadrant multiplier has a single ended current output which eliminates the extra summation circuit at the output of the neuron that reduces the chip area as well as power consumption. In addition, programmability of activation function improves the neural network design process while enables the proposed neuron circuit to be used properly in learning algorithms such as back propagation. The most important feature of the proposed circuit is low power consumption and simple circuit topology. The performance of the circuit is confirmed by HSPICE simulations using 0.18 μm CMOS technology parameters. The circuit operates at 1 V supply voltage and consumes only 15 μW. Finally, different neural networks are realized using the proposed neuron circuit, which are successfully used to solve exclusive OR (XOR) problem and region classification problem to verify the accuracy and performance of the proposed circuit.

A new guard ring for radiation induced noise reduction in photodiodes implemented in 0.18 μm CMOS technology

A new p-type guard ring by introduction of a thin p-type layer which encloses shallow trench isolation (STI) layer is utilized to reduce radiation induced noise in photodiodes implemented in 0.18 $$\upmu$$ m standard complementary-metal-oxide-semiconductor (CMOS) technology. The guard ring efficiency is characterized according to a new radiation model developed for p–n photodiodes implemented in the same technology. The extracted model which is the oxide trapped charges and interface state values is verified using a simulation setup for two different structures. The optimized guard ring with the doping concentration of $$10^{+19}$$ atoms cm $$^{-3}$$ reduces the dark current of photodiodes at 1 Mrad dose of ionizing radiation from $$6.97\,\times \,10^{-13}$$ A (without the guard ring) to $$1.29\,\times \,10^{-14}$$ A for STI in contact with the active region structure and from $$5.95\,\times \,10^{-13}$$ A (without the guard ring) to $$2\,\times \,10^{-14}$$ A for STI surrounded p-well structure. The proposed guard ring can be used as a promising structure for ionizing radiation hardening of photodiodes.