Design of a new CMOS Low-Power Analogue Neuron

Abstract

In this paper, a low-power analogue complementary metal oxide semiconductor (CMOS) artificial neuron circuit is presented. The analogue neuron is composed of multiplier and programmable activation function circuits. The proposed four-quadrant multiplier has a single ended current output which eliminates the extra summation circuit at the output of the neuron that reduces the chip area as well as power consumption. In addition, programmability of activation function improves the neural network design process while enables the proposed neuron circuit to be used properly in learning algorithms such as back propagation. The most important feature of the proposed circuit is low power consumption and simple circuit topology. The performance of the circuit is confirmed by HSPICE simulations using 0.18 μm CMOS technology parameters. The circuit operates at 1 V supply voltage and consumes only 15 μW. Finally, different neural networks are realized using the proposed neuron circuit, which are successfully used to solve exclusive OR (XOR) problem and region classification problem to verify the accuracy and performance of the proposed circuit.