Μm Complementary Metal Oxide Semiconductor Process Research Articles

Design of SEE-Tolerant analog switch chip with a novel diode structure *

This paper proposes a novel circuit-level design in order to enhance the radiation tolerance of an analog switch integrated circuit. After analyzing the mechanisms of single-particle sensitivity in a high-voltage analog switch chip fabricated using a commercial 1 μm complementary metal–oxide–semiconductor process, a diode unit was employed to reduce the V GS (voltage between the gate and the base) of the parasitic triode within the metal–oxide–semiconductor field-effect transistor of the switch. This reduction lowered the probability of activating the parasitic triode in response to single-event effect (SEE). Subsequently, single-particle irradiation experiments proceeded with the high-voltage analog switch chip, both with and without the diode unit. In the unreinforced device, the current of the power supply reached 100 mA within 11 s of single-particle irradiation at 75.8 MeV•cm2 mg−1. In contrast, in the reinforced device, the current of the power supply remained relatively stable under irradiation at both 37.2 and 75.8 MeV•cm2 mg−1. These findings indicate that the reinforced analog switch chip exhibits an SEE tolerance exceeding 75.8 MeV•cm2 mg−1, highlighting its potential to enhance the radiation tolerance of analog switches.

An 8 bit-ENOB Sampling-rate Reconfigurable Asynchronous SAR ADC with Metastability Watchdog Circuit for Activity-driven Multi-Channel CMOS Readout ASICs for Space Applications

This article presents an innovative architecture and design of an 8-bits Effective-Number-of-Bits (ENOB) Asynchronous Successive-Approximation-Register (ASAR) Analog-to-Digital-Converter (ADC), aiming at activity-driven multi-channel Complementary-Metal-Oxide-Semiconductor (CMOS) readout Application-Specific-Integrated-Circuits (ASICs) for imaging and spectroscopic applications in space field. The proposed ADC needs only a single low duty-cycle clock signal ‘CLKSampling’ to initiate the conversion process and generates all other required clock signals internally. Unlike conventional ASAR ADCs, this ADC makes use of a unique rising edge only variable delay-cell to introduce desired delay values to the internally generated clock signal. In addition, the ADC features sampling-rate (fs)-reconfigurability, from typical 40 kHz to 167 kHz, with a proportional power consumption. Also, the proposed architecture is flexible with respect to the time-period and duty-cycle of the ‘CLKSampling’ signal, that can be tailored keeping in view the primary requirements of the desired applications. Moreover, the proposed design is equipped with a simple metastability watchdog circuitry. Fabricated in a 0.35 µm CMOS process at 3.3 V supply, the ADC secures a measured ENOB, and Signal-to-Noise-and-Distortion-Ratio (SNDR) of 7.76-bits, and 48.47 dB, respectively at the typical fs of 40 kHz. Measured Integral-Non-Linearity (INL), and Differential-Non-Linearity (DNL) are within one LSB. The ADC normalized figure-of-merit (FoMWN) - proposed to fairly compare high voltage-based ADCs with low voltage-based ADCs - is 476 fJ/C-step at its maximum fs with all the sections of the ADC operating at 3.3 V. The FoMWN improves to 261.7 fJ/c-step and 243 fJ/c-step with the digital section and delay-cell operated at 1.2 V with and without level-shifters power contribution, respectively without any performance deterioration.

An Area-Efficient up/down Double-Sampling Circuit for a LOFIC CMOS Image Sensor.

A lateral overflow integration capacitor (LOFIC) complementary metal oxide semiconductor (CMOS) image sensor can realize high-dynamic-range (HDR) imaging with combination of a low-conversion-gain (LCG) signal for large maximum signal electrons and a high-conversion-gain (HCG) signal for electron-referred noise floor. However, LOFIC-CMOS image sensor requires a two-channel read-out chain for LCG and HCG signals whose polarities are inverted. In order to provide an area-efficient LOFIC-CMOS image sensor, a one-channel read-out chain that can process both HCG and LCG signals is presented in this paper. An up/down double-sampling circuit composed of an inverting amplifier for HCG signals and a non-inverting attenuator for LCG signals can reduce the area of the read-out chain by half compared to the conventional two-channel read-out chain. A test chip is fabricated in a 0.18 μm CMOS process with a metal-insulator-metal (MIM) capacitor, achieving a readout noise of 130 μVrms for the HCG signal and 1.19 V for the LCG input window. The performance is equivalent to 103 dB of the dynamic range with our previous LOFIC pixel in which HCG and LCG conversion gains are, respectively, 160 μV/e- and 10 μV/e-.

Ambient light rejection method for multiphoton coincidence detection in single-photon avalanche diode-based DToF sensors.

This paper presents an adaptive control method used for multiphoton coincidence detection to reduce the effect of ambient light that exists in accessing flight time. Behavioral and statistical models are used to demonstrate the working principle with MATLAB, and the method is achieved through a compact circuit. The adaptive coincidence detection in accessing flight time achieves a higher probability of 66.5% than fixed parameter coincidence detection's 46%, while ambient light intensity is 75klux. Additionally, it also can achieve a dynamic detection range 43.8 times higher than the fixed parameter detection. The circuit is designed in 0.11µm complementary metal-oxide semiconductor process, and the area consumption is 0.00178m m 2. The postsimulation experiment through Virtuoso shows that the histogram of coincidence detection under adaptive control circuit is consistent with the behavioral model. The proposed method acieves the coefficient of variance as 0.0495 smaller than fixed parameter coincidence's 0.0853, which means better ambient light tolerance in accessing flight time for three-dimensional imaging.

Supply less sensitive ring voltage-controlled oscillator for microwave L-band frequencies

PurposeThe primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.Design/methodology/approachFirst, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.FindingsThis work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm2 compared to contemporary designs.Originality/valueThe proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

Thermoelectric Energy Micro Harvesters with Temperature Sensors Manufactured Utilizing the CMOS-MEMS Technique.

This study develops a TEMH (thermoelectric energy micro harvester) chip utilizing a commercial 0.18 μm CMOS (complementary metal oxide semiconductor) process. The chip contains a TEMH and temperature sensors. The TEMH is established using a series of 54 thermocouples. The use of the temperature sensors monitors the temperature of the thermocouples. One temperature sensor is set near the cold part of the thermocouples, and the other is set near the hot part of the thermocouples. The performance of the TEMH relies on the TD (temperature difference) at the CHP (cold and hot parts) of the thermocouples. The more the TD at the CHP of the thermocouples increases, the higher the output voltage and output power of the TEMH become. To obtain a higher TD, the cold part of the thermocouples is designed as a suspended structure and is combined with cooling sheets to increase heat dissipation. The cooling sheet is constructed of a stack of aluminum layers and is mounted above the cold part of the thermocouple. A finite element method software, ANSYS, is utilized to compute the temperature distribution of the TEMH. The TEMH requires a post-process to obtain the suspended thermocouple structure. The post-process utilizes an RIE (reactive ion etch) to etch the two sacrificial materials, which are silicon dioxide and silicon substrate. The results reveal that the structure of the thermocouples is completely suspended and does not show any injury. The measured results reveal that the output voltage of the TEMH is 32.5 mV when the TD between the CHP of the thermocouples is 4 K. The TEMH has a voltage factor of 8.93 mV/mm2K. When the TD between the CHP of the thermocouples is 4 K, the maximum output power of the TEMH is 4.67 nW. The TEMH has a power factor of 0.31 nW/mm2K2.

Un nuevo rectificador reconfigurable CMOS para recolectores de energía piezoeléctrica en dispositivos portables

Wearable energy harvesters have potential application in the conversion of human-motion energy into electrical energy to power smart health-monitoring devices, the textile industry, smartwatches, and glasses. These energy harvesters require optimal rectifier circuits that maximize their charging efficiencies. In this study, we present the design of a novel complementary metal-oxide semiconductor (CMOS) reconfigurable rectifier for wearable piezoelectric energy harvesters that can increase their charging efficiencies. The designed rectifier is based on standard 0.18 µm CMOS process technology considering a geometrical pattern with a total silicon area of 54.765 µm x 86.355 µm. The proposed rectifier circuit has two transmission gates (TG) that are composed of four rectifier transistors with a charge of 45 kΩ, a minimum input voltage of 500 mV and a maximum voltage of 3.3 V. Results of numerical simulations of the rectifier performance indicate a voltage conversion efficiency of 99.4% and a power conversion efficiency up to 63.3%. The proposed rectifier can be used to increase the charging efficiency of wearable piezoelectric energy harvesters.

An ultralow-power CMOS bandgap voltage reference with N+ doped PMOS

An ultra-low-power and low-area complementary metal oxide semiconductor (CMOS) bandgap voltage reference, without resistor and substrate bipolar, is presented and verified in the TSMC 0.18 μm CMOS process in this paper. By adopting PMOS transistor with N+ doped gate and a new temperature compensation technique, the proposed bandgap demonstrates a power consumption of around 50 nA for a supply voltage of 1.5 V and a temperature coefficient of 75 ppm without trimming. The chip can operate with a supply voltage from 1.2 V to 1.8 V and small area of the bandgap is around 0.001 mm2. The characteristic of the proposed voltage bandgap reference makes it suitable for ultralow-power low-area applications.

On-Chip Cyclic Voltammetry Measurements Using a Compact 1024-Electrode CMOS IC.

Complementary metal–oxide–semiconductor (CMOS) microelectrode arrays integrate amplifier arrays with on-chip electrodes, offering high-throughput platforms for electrochemical sensing with high spatial and temporal resolution. Such devices have been developed for highly parallel constant voltage amperometric detection of transmitter release from multiple cells with single-vesicle resolution. Cyclic voltammetry (CV) is an electrochemical method that applies voltage waveforms, which provides additional information about electrode properties and about the nature of analytes. A 16-channel, 64-electrode-per-channel CMOS integrated circuit (IC) fabricated in a 0.5 μm CMOS process for CV is demonstrated. Each detector consists of only 11 transistors and an integration capacitor with a unit dimension of 0.0015 mm2. The device was postfabricated using Pt as the working electrode material with a shifted electrode design, which makes it possible to redefine the size and the location of working electrodes. The system incorporating cell-sized (8 μm radius) microelectrodes was validated with dopamine injection tests and CV measurements of potassium ferricyanide at a 1 V/s scanning rate. The cyclic voltammograms were in excellent agreement with theoretical predictions. The technology enables rigorous characterization of electrode performance for the application of CMOS microelectrode arrays in low-noise amperometric measurements of quantal transmitter release as well as other biosensing applications.

Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs

This paper presents inductance simulators using the voltage differencing differential input buffered amplifier (VD-DIBA) as an active building block. Three types of inductance simulators, including floating lossless inductance, series inductance-resistance, and parallel inductance-resistance simulators, are proposed, in addition to their application to the 4th order elliptic lowpass ladder filter. The simple design procedures of these inductance simulators using a circuit block diagram are also given. The proposed inductance simulators employ two VD-DIBAs and two passive elements. The complementary metal oxide semiconductor (CMOS) VD-DIBA used in this design utilizes the multiple-input metal oxide semiconductor (MOS) transistor technique in order to achieve a compact and simple structure with a minimum count of transistors. Thanks to this technique, the VD-DIBA offers high performances compared to the other CMOS structures presented in the literature. The CMOS VD-DIBAs and their applications are designed and simulated in the Cadence environment using a 0.18 µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). Using a supply voltage of ±0.9 V, the linear operation of VD-DIBA is obtained over a differential input range of −0.5 V to 0.5 V. The lowpass (LP) ladder filter realized with the proposed inductance simulators shows a dynamic range (DR) of 80 dB for a total harmonic distortion (THD) of 2% at 1 kHz and a 1.8 V peak-to-peak output. In addition, the experimental results of the floating inductance simulators and their applications are obtained by using VD-DIBA constructed from the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental ones, confirming the advantages of the inductance simulators and their application.

A Novel Ultrasonic TOF Ranging System Using AlN Based PMUTs.

This paper presents a high-accuracy complementary metal oxide semiconductor (CMOS) driven ultrasonic ranging system based on air coupled aluminum nitride (AlN) based piezoelectric micromachined ultrasonic transducers (PMUTs) using time of flight (TOF). The mode shape and the time-frequency characteristics of PMUTs are simulated and analyzed. Two pieces of PMUTs with a frequency of 97 kHz and 96 kHz are applied. One is used to transmit and the other is used to receive ultrasonic waves. The Time to Digital Converter circuit (TDC), correlating the clock frequency with sound velocity, is utilized for range finding via TOF calculated from the system clock cycle. An application specific integrated circuit (ASIC) chip is designed and fabricated on a 0.18 μm CMOS process to acquire data from the PMUT. Compared to state of the art, the developed ranging system features a wide range and high accuracy, which allows to measure the range of 50 cm with an average error of 0.63 mm. AlN based PMUT is a promising candidate for an integrated portable ranging system.

Research on High-Resolution Miniaturized MEMS Accelerometer Interface ASIC.

High-precision microelectromechanical system (MEMS) accelerometers have wide application in the military and civil fields. The closed-loop microaccelerometer interface circuit with switched capacitor topology has a high signal-to-noise ratio, wide bandwidth, good linearity, and easy implementation in complementary metal oxide semiconductor (CMOS) process. Aiming at the urgent need for high-precision MEMS accelerometers in geophones, we carried out relevant research on high-performance closed-loop application specific integrated circuit (ASIC) chips. According to the characteristics of the performance parameters and output signal of MEMS accelerometers used in geophones, a high-precision closed-loop interface ASIC chip based on electrostatic time-multiplexing feedback technology and proportion integration differentiation (PID) feedback control technology was designed and implemented. The interface circuit consisted of a low-noise charge-sensitive amplifier (CSA), a sampling and holding circuit, and a PID feedback circuit. We analyzed and optimized the noise characteristics of the interface circuit and used a capacitance compensation array method to eliminate misalignment of the sensitive element. The correlated double sampling (CDS) technology was used to eliminate low-frequency noise and offset of the interface circuit. The layout design and engineering batch chip were fabricated by a standard 0.35 μm CMOS process. The active area of the chip was 3.2 mm × 3 mm. We tested the performance of the accelerometer system with the following conditions: power dissipation of 7.7 mW with a 5 V power supply and noise density less than 0.5 μg/Hz1/2. The accelerometers had a sensitivity of 1.2 V/g and an input range of ±1.2 g. The nonlinearity was 0.15%, and the bias instability was about 50 μg.

Research on a CMOS-MEMS Infrared Sensor with Reduced Graphene Oxide

In this research, a new application of reduced graphene oxide (rGO) for a complementary metal-oxide-semiconductor (CMOS)-MEMS infrared (IR) sensor and emitter is proposed. Thorough investigations of IR properties including absorption and emission were proceeded with careful calibration and measurement with a CMOS thermoelectric sensor. The thermocouples of the sensor consist of aluminum and n-polysilicon layers which are fabricated with the TSMC 0.35 μm CMOS process and MEMS post-process. In order to improve the adhesion of rGO, a sensing area at the center of the membrane is formed with an array of holes, which is easy for the drop-coating of rGO material upon the sensing region. To evaluate the performance of the IR sensor with rGO, different conditions of the IR thermal radiation experiments were arranged. The results show that the responsivity of our proposed CMOS-MEMS IR sensor with rGO increases by about 77% compared with the sensor without rGO. For different IR absorption incident angles, the measurement of field of view shows that the CMOS-MEMS IR sensor with rGO has a smaller view angle, which can be applied for the application of long-distance measuring. In addition, characteristics of the proposed thermopile are estimated and analyzed with comparisons to the available commercial sensors by the experiments.

Simulation of High-Speed and Low-Power CMOS Binary Image Sensor Based on Gate/Body-Tied PMOSFET-Type Photodetector Using Double-Tail Comparator

In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for highspeed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 μm CMOS process.

A High-Temperature, Low-Noise Readout ASIC for MEMS-Based Accelerometers.

This paper presents the development and measurement results of a complementary metal oxide semiconductor (CMOS) readout application-specific integrated circuit (ASIC) for bulk-silicon microelectromechanical system (MEMS) accelerometers. The proposed ASIC converts the capacitance difference of the MEMS sensor into an analog voltage signal and outputs the analog signal with a buffer. The ASIC includes a switched-capacitor analog front-end (AFE) circuit, a low-noise voltage reference generator, and a multi-phase clock generator. The correlated double sampling technique was used in the AFE circuits to minimize the low-frequency noise of the ASIC. A programmable capacitor array was implemented to compensate for the capacitance offset of the MEMS sensor. The ASIC was developed with a 0.18 μm CMOS process. The test results show that the output noise floor of the low-noise amplifier was −150 dBV/√Hz at 100 Hz and 175 °C, and the sensitivity of the AFE was 750 mV/pF at 175 °C. The output noise floor of the voltage reference at 175 °C was −133 dBV/√Hz at 10 Hz and −152 dBV/√Hz at 100 Hz.

A CMOS Low Pass Filter for SoC Lock-in-Based Measurement Devices.

This paper presents a fully integrated Gm–C low pass filter (LPF) based on a current steering Gm reduction-tuning technique, specifically designed to operate as the output stage of a SoC lock-in amplifier. To validate this proposal, a first-order and a second-order single-ended topology were integrated into a 1.8 V to 0.18 µm CMOS (Complementary Metal-Oxide-Semiconductor) process, showing experimentally a tuneable cutoff frequency that spanned five orders of magnitude, from tens of mHz to kHz, with a constant current consumption (below 3 µA/pole), compact size (<0.0140 mm2/pole), and a dynamic range better than 70 dB. Compared to state-of-the-art solutions, the proposed approach exhibited very competitive performances while simultaneously fully satisfying the demanding requirements of on-chip portable measurement systems in terms of highly efficient area and power. This is of special relevance, taking into account the current trend towards multichannel instruments to process sensor arrays, as the total area and power consumption will be proportional to the number of channels.

Design of a low-power 12.5Gb/s 1:10 demultiplexer in 0.18μm CMOS*

A low-power 12.5Gb/s 1:10 Demultiplexer (DEMUX) without inductors is designed in 0.18μm CMOS (Complementary metal oxide semiconductor) process. The 1:10 DEMUX includes a high-speed 1:2 DEMUX, two serial low-speed 1:5 DEMUX, a 5 frequency divider and so on. The latch of the high-speed 1:2 DEMUX adopts the CML (Current Mode Logic) structure. The rest of the triggers all use E-TSPC(Extended True Single Phase Clock)structure. In the design of the 5 frequency divider, the logic gate circuit is embedded in flip-flop to improve the work frequency. The post simulated result shows that when the data rate of the input pseudorandom is 12.5Gb/s and the clock frequency is 6.25GHz at a supply voltage of 1.8V, this1:10 DEMUX can work well and the eye diagram of output data is clear. The output swing is 400mV on an external 50 Ohm load and the total power dissipation is 200mW. The die size is 0.64×0.57mm2.

Three‐bit 2–18 GHz all‐pass network‐based trombone phase delay line with improved insertion loss variation

A complementary metal–oxide–semiconductor (CMOS) trombone true-time delay (TTD) operating from 2 to 18 GHz is presented. The second-order all-pass network (APN) is used to construct the delay lines. The higher-order delay response of the APN allows for a better trade-off between the delay and bandwidth compared to the artificial transmission line structures. The all-pass characteristic of the APN further improves the matching performance of the TTD. In order to improve the insertion loss (IL) variations between different delay states, the source degeneration by resistor–capacitor structure is used for the switching amplifiers. Two 3-bit TTDs are fabricated in a standard 0.13 µm CMOS process, namely TTD 1 and TTD 2. TTD 1 is based on conventional switching amplifiers and TTD 2 adopts the proposed source degeneration technique. The measurement results show that the root-mean-square IL variation of TTD 1 and TTD 2 is better than 2 and 1.4 dB. The input and output return loss of the two TTDs is >12 dB. Delays of 270 and 265 ps are achieved by TTD 1 and TTD 2. The power consumption for TTD 1 is 2–6.2 mW and is 2–3.6 mW for TTD 2.

Thermal stress analysis for a CMOS-MEMS microphone with various metallization and materials

Many micro-electromechanical systems (MEMS) microphone structures are developing along with the growing market of portable and smart devices. Therein, the impact of thermal loading is one of the inevitable concerns that need to be considered from the viewpoint of microphone's reliability. This study focused on the thermal stress analysis for a complementary metal oxide semiconductor (CMOS)-MEMS microphone with various metallization and materials in diaphragm and back-plate under thermal loading; meanwhile, the weak points in the microphone structure under thermal loading were identified through simulation and experiment. In simulation, three-dimensional finite element (FE) models of the MEMS microphone with different metallization and materials in the diaphragm, including aluminum and copper, were built by commercial software ANSYS. The FE models were subjected to the thermal loading from −40 °C to 125 °C. In experiment, the failure mode of a CMOS-MEMS microphone chip by TSMC (Taiwan Semiconductor Manufacturing Company Limited) 0.18 μm CMOS process after 500 cycles of thermal loading from −40 °C to 125 °C was analyzed using the images obtained from scanning electron microscope (SEM). The results from simulation are consistent with those from experiment. The stress at the interface of the metal located at the bottom of diaphragm is higher than that at its top according to FE analysis and the stress concentration was found at the interface between the diaphragm and Si substrate in the microphone. The SEM images showed the delamination and crack locations of the microphone after thermal cycling test agreed with those from FE analysis. Moreover, diverse metallization and materials were studied by FE analysis for structural enhancement of the microphone. The results indicated that adopting Cu layer instead of Al layer in the diaphragm could decrease the thermal stress around 33% when under thermal loading. The weak spots of the CMOS MEMS microphone chip were found in this study and an effective enhanced approach was proposed for this microphone structure with alternative metallization and material.

A 0.0014 mm2 150 nW CMOS Temperature Sensor with Nonlinearity Characterization and Calibration for the -60 to +40 °C Measurement Range.

This work presents a complementary metal–oxide–semiconductor (CMOS) ultra-low power temperature sensor chip for cold chain applications with temperatures down to −60 °C. The sensor chip is composed of a temperature-to-current converter to generate a current proportional to the absolute temperature (PTAT), a current controlled oscillator to convert the current to a frequency signal, and a counter as the frequency-to-digital converter. Unlike the conventional linear error calibration method, the nonlinear error of the PTAT current under the low temperature range is fully characterized based on the device model files provided by the foundry. Simulation has been performed, which clearly shows the nonlinear model is much more accurate than the linear model. A nonlinear error calibration method, which requires only two-point calibration, is then proposed. The temperature sensor chip has been designed and fabricated in a 0.13 μm CMOS process, with a total active die area of 0.0014 mm2. The sensor only draws a 140 nA current from a 1.1 V supply, with the key transistors working in the deep subthreshold region. Measurement results show that the proposed nonlinear calibration can decrease the measurement error from −0.9 to +1.1 °C for the measurement range of −60 to +40 °C, in comparison with the error of −1.8 to +5.3 °C using the conventional linear error calibration.