Three‐bit 2–18 GHz all‐pass network‐based trombone phase delay line with improved insertion loss variation

Abstract

A complementary metal–oxide–semiconductor (CMOS) trombone true-time delay (TTD) operating from 2 to 18 GHz is presented. The second-order all-pass network (APN) is used to construct the delay lines. The higher-order delay response of the APN allows for a better trade-off between the delay and bandwidth compared to the artificial transmission line structures. The all-pass characteristic of the APN further improves the matching performance of the TTD. In order to improve the insertion loss (IL) variations between different delay states, the source degeneration by resistor–capacitor structure is used for the switching amplifiers. Two 3-bit TTDs are fabricated in a standard 0.13 µm CMOS process, namely TTD 1 and TTD 2. TTD 1 is based on conventional switching amplifiers and TTD 2 adopts the proposed source degeneration technique. The measurement results show that the root-mean-square IL variation of TTD 1 and TTD 2 is better than 2 and 1.4 dB. The input and output return loss of the two TTDs is >12 dB. Delays of 270 and 265 ps are achieved by TTD 1 and TTD 2. The power consumption for TTD 1 is 2–6.2 mW and is 2–3.6 mW for TTD 2.