Μm Complementary Metal Oxide Semiconductor Process Research Articles

Widely tunable low‐pass g m − C filter for biomedical applications

This study presents a fourth-order, low-pass Butterworth transconductor–capacitor filter with tunable bandwidth for biomedical signal processing front-ends. An architecture has been proposed for realising very low transconductance values with tunability. This transconductor architecture makes it possible to realise a fully differential filter without the need for explicit common-mode feedback circuit. The filter has two tuning schemes, a resistor-based tuning ( R -tuning) and a switched transconductor-based tuning ( D -tuning). With R -tuning, the bandwidth is adjustable between 1 and 70 Hz and with D -tuning, the tuning range is 30 mHz–100 Hz. The filter has been designed in united microelectronics corporation (UMC) 0.18 µm complementary metal–oxide–semiconductor process. In terms of figure-of-merit, the proposed filter is found to be on par with the filters reported in the literature.

Integrated Optoelectronic Position Sensor for Scanning Micromirrors.

Scanning micromirrors have been used in a wide range of areas, but many of them do not have position sensing built in, which significantly limits their application space. This paper reports an integrated optoelectronic position sensor (iOE-PS) that can measure the linear displacement and tilting angle of electrothermal MEMS (Micro-electromechanical Systems) scanning mirrors. The iOE-PS integrates a laser diode and its driving circuits, a quadrant photo-detector (QPD) and its readout circuits, and a band-gap reference all on a single chip, and it has been fabricated in a standard 0.5 μm CMOS (Complementary Metal Oxide Semiconductor) process. The footprint of the iOE-PS chip is 5 mm × 5 mm. Each quadrant of the QPD has a photosensitive area of 500 µm × 500 µm and the spacing between adjacent quadrants is 500 μm. The iOE-PS chip is simply packaged underneath of an electrothermally-actuated MEMS mirror. Experimental results show that the iOE-PS has a linear response when the MEMS mirror plate moves vertically between 2.0 mm and 3.0 mm over the iOE-PS chip or scans from −5 to +5°. Such MEMS scanning mirrors integrated with the iOE-PS can greatly reduce the complexity and cost of the MEMS mirrors-enabled modules and systems.

Fully integrated CMOS power amplifier using resistive current combining technique

This study presents a fully integrated complementary metal oxide semiconductor (CMOS) power amplifier (PA) covering LTE-advanced bands from 825 to 915 MHz for cellular application and the bands of 978 MHz universal access transceiver mode and 1090 MHz extended squitter mode of an automatic dependent surveillance-broadcast transmitter for the unmanned aircraft system. The 3.63 mm × 0.95 mm PA including all on-chip input and output matching networks, fabricated using the 0.18 μm CMOS process exhibits peak output power of 24 dBm, modulated output power of >22 dBm at 978 MHz, the maximum power gain of 27 dB and bandwidth of 290 MHz.

Positive feedback technique and split‐length transistors for DC‐gain enhancement of two‐stage op‐amps

This study presents the design and simulation of a fully differential two‐stage op‐amp in a 0.18 μm complementary metal–oxide–semiconductor process with a 1.8 V supply voltage. In this op‐amp, positive feedback technique and split‐length transistors (SLTs) are employed to increase the DC‐gain of the op‐amp by about 22 dB without affecting the unity‐gain bandwidth (UGBW), stability, power dissipation and output voltage swing of the conventional two‐stage op‐amp. A comprehensive analysis is provided for differential‐mode gain, common‐mode gain, power supply rejection ratio, input‐referred noise, input offset, frequency response and the effect of using SLTs on DC‐gain sensitivity. The proposed op‐amp is utilised in a flip‐around sample‐and‐hold amplifier (SHA). The output spectrum of the SHA shows the total harmonic distortion of 0.0023%. The post‐layout and Monte Carlo simulation results show that the proposed op‐amp has better performance than the state‐of‐the‐art designs.

An amplifier‐offset‐insensitive and high PSRR subthreshold CMOS voltage reference

SummaryAn amplifier‐offset‐insensitive complementary metal‐oxide‐semiconductor (MOS) voltage reference (CVR) circuit with high power supply ripple rejection (PSRR) is presented. Due to the novel structure of employing subthreshold MOS transistors, the proposed CVR circuit can suppress the direct current offset effects of the internal amplifier. Design considerations in optimizing the power and area consumptions and improving the PSRR are presented. The proposed CVR circuit is implemented in a standard 0.18 μm complementary MOS process. Measured results show that the reference can run with down‐to 0.9 V supply voltage, while the power consumption is only 70 nW. The measured PSRR is better than −37 dB over the full frequency range.

Compact and Broadband Variable True-Time Delay Line with DLL-Based Delay-Time Control

This study presents the design and implementation of a compact and wideband active variable true-time delay line for timed array applications. Using a combination of coarse delay cells and fine delay cells, the proposed delay line achieves a large delay range and a high delay tuning resolution. Instead of LC delay lines or transmission lines, the delay can be approximated by compact active filters using transconductors and capacitors. The coarse delay cell adopts inductive peaking to broaden the bandwidth, and the fine delay cell employs a novel differential active inductor to improve the delay resolution and integration level. The group delays of the coarse delay cells and fine delay cells are analyzed and optimized. The signal transmission path is controlled by path-selection amplifiers and V---I conversion switches to achieve delay variability. The delay time is calibrated by the delay-locked loop (DLL) to mitigate the process, voltage and temperature variations. The complementary metal-oxide-semiconductor (CMOS) variable true-time delay line is fabricated in a 0.18-$$\upmu \hbox {m}$$μm CMOS process. Experiments indicate that the maximal relative delay is 95?ps and that the delay resolution is 5?ps within a 10% delay variation over a frequency range of 0.6---4.2?GHz. The chip dissipates 88?mW under a 1.8-V supply, and the core area including the DLL circuit is only 0.05?$$\hbox { mm}^{2}$$mm2.

A 300‐mA load CMOS low‐dropout regulator without an external capacitor for SoC and embedded applications

SummaryThis study proposes a 300‐mA external capacitor‐free low‐dropout (LDO) regulator for system‐on‐chip and embedded applications. To achieve a full‐load range from 0 to 300 mA, a two‐scheme (a light‐load case and a heavy‐load case) operation LDO regulator with a novel control circuit is proposed. In the light‐load case (0–0.5 mA), only one P‐type metal–oxide–semiconductor input‐pair amplifier with a 10‐pF on‐chip capacitor is used to obtain a load current as low as 0. In the heavy‐load case (0.5 to 300 mA), both P‐type metal–oxide–semiconductor and N‐type metal–oxide–semiconductor differential input‐pair amplifiers with an assistant push‐pull stage are utilized to improve the stability of the LDO regulator and achieve a high slew rate and fast‐transient response. Measurements show an output voltage of 3.3 V and a full output load range from 0 to 300 mA. A line regulation of 1.66 mV/V and a load regulation of 0.0334 mV/mA are achieved. The measured power‐supply rejection ratio at 1 kHz is −65 dB, and the measured output noise is only 34 μV. The total active chip size is approximately 0.4 mm2 with a standard 0.5 μm complementary metal–oxide–semiconductor process. Copyright © 2017 John Wiley & Sons, Ltd.

A Low Power Low Phase Noise Oscillator for MICS Transceivers.

A low-power, low-phase-noise quadrature oscillator for Medical Implantable Communications Service (MICS) transceivers is presented. The proposed quadrature oscillator generates 349~689 MHz I/Q (In-phase and Quadrature) signals covering the MICS band. The oscillator is based on a differential pair with positive feedback. Each delay cell consists of a few transistors enabling lower voltage operation. Since the oscillator is very sensitive to disturbances in the supply voltage and ground, a self-bias circuit for isolating the voltage disturbance is proposed to achieve bias voltages which can track the disturbances from the supply and ground. The oscillation frequency, which is controlled by the bias voltages, is less sensitive to the supply and ground noise, and a low phase noise is achieved. The chip is fabricated in the UMC (United Microelectronics Corporation) 0.18 μm CMOS (Complementary Metal Oxide Semiconductor) process; the core just occupies a 28.5 × 22 μm2 area. The measured phase noise is −108.45 dBc/Hz at a 1 MHz offset with a center frequency of 540 MHz. The gain of the oscillator is 0.309 MHz/mV with a control voltage from 0 V to 1.1 V. The circuit can work with a supply voltage as low as 1.2 V and the power consumption is only 0.46 mW at a 1.8 V supply voltage.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

0.97 mW/Gb/s, 4 Gb/s CMOS clock and data recovery IC with dynamic voltage scaling

This paper presents a low-power complementary metal–oxide–semiconductor (CMOS) clock and data recovery (CDR) integrated circuit (IC) with dynamic voltage scaling (DVS) technique. When DVS is adopted, the power efficiency can be improved by selecting the low supply voltage as possible for a given bit rate. However, the supply voltage generated from a switching regulator such as a buck converter has the ripple voltage at the switching frequency so that the CDR performance may be degraded accordingly. Thus, in this study, the analysis on the relationship among the ripple voltage, the switching frequency and the jitter tolerance (JTOL) is carried out and the appropriate ripple voltage and switching frequency of the buck converter are chosen based on the analysis. Moreover, low supply voltage circuit techniques are carefully utilised for the design of the low-power CDR IC. The CDR IC, implemented in a 0.11 μm CMOS process, shows the power efficiency of 0.97 mW/Gb/s at 4 Gb/s including the buck converter. When 4 Gb/s 231−1 pseudorandom binary sequence is used, the measured bit error rate is better than 10−12, the measured JTOL is 0.3 UIpp and the measured jitter of the recovered clock is 6.1 psrms.

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

ABSTRACTThis article presents a reconfigurable pipeline analog-to-digital converter (ADC) using a two-stage cyclic configuration. The ADC consists of two stages with 1.5 effective bit resolution, two reference circuits for voltage and current biasing, and a clock generator and timing circuit. Throughout the development of this ADC, several techniques were combined for reducing the power consumption as well as for preserving the converter linearity. To reduce the power consumption, the circuit has a single operational trans-conductance amplifier shared by both pipeline stages. To keep conversion linearity, circuits such as the bootstrapped complementary metal-oxide semiconductor (CMOS) transmission gates and a robust comparator topology were implemented. The circuit can be configured to perform conversion between 7 and 15 bit resolutions, and it works with the master clock frequency in the range of 1 kHz to 40 MHz. The circuit has been prototyped in a 3.3 V 0.35 µm CMOS process and consumes 14.1 mW at 40 MHz and 8 MSample/s sampling rate. With this resolution and sampling rate, it achieves 60.1 dB SNR, 56.57 dB SINAD and 9.1 bit ENOB at 0.666 MHz input frequency and 53.6 dB SNR, 52.4 dB SINAD and 8.6 bit ENOB at 3.85 MHz input frequency. The technological FOM obtained was 13.2 A s/m2.

Ultra‐low power current mode all‐ MOS ASK demodulator for radio frequency identification applications

An ultra-low power amplitude shift keying (ASK) demodulator for radio frequency identification (RFID) tags is presented. On the basis of a fast averaging stage, the proposed ASK-demodulator uses a current domain switching envelope amplifier which yields low-power operation. More importantly, it removes the need for a conventional voltage comparator. Designed and fabricated in a 0.18 µm complementary metal–oxide–semiconductor process on about 3000 µm2 silicon area, the proposed demodulator consumes only 7.5 µA from a magnetically coupled induced power. Operating with a 13.56 MHz carrier frequency, the circuit supports modulation indices from 7 up to 100%. The demodulator may as well be used in passive biomedical devices where power efficiency is crucial.

A high-resolution multi-phase delay-locked loop with offset locking technique

ABSTRACTIn this work, we propose a new type of high-resolution delay-locked loop (DLL) which achieves the performance of high-resolution output by offset locking techniques without restrictions of intrinsic delay in the delay cell. Compared to traditional multi-phase clock generator, this architecture has the features of small size, low jitters, low-power consumption and high resolution. This DLL has been fabricated in 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The measured root-mean-square and peak-to-peak jitters are 2.89 ps and 31.1 ps at 250 MHz, respectively. The power dissipation is 68 mW for a supply voltage of 3.3 V. The maximum resolution of this work is 144 p and the intrinsic delay of 0.35 μm CMOS process is 220 ps. Comparing with intrinsic delay, the improvement of maximum resolution is 34.5%.

Wide-temperature range CMOS capacitance to digital convertor for MEMS pressure sensors

We present a complementary metal-oxide-semiconductor (CMOS) capacitance to digital converter (CDC) for capacitive Microelectromechanical Systems (MEMS) pressure sensors, that is functionally tested over a wide temperature range from −20°C to 225°C. The proposed circuit uses a sigma–delta technique to convert the input ratio between sensor and reference capacitors into a digital output. A constant-gm biasing technique is used to alleviate performance degradation at high temperatures. The circuit is implemented using the IBM 0.13μm CMOS process technology which incorporates a 2.5V power supply. The simulation results show that the circuit offers 0.03% accuracy between −55°C and 225°C. The circuit is tested with a commercial MEMS capacitive pressure sensor. Experimental results show that the circuit offers good temperature stability, resolution of 1.44fF, and accuracy of 2.4% between −20°C and 225°C.

Current estimation circuit for discontinuous conduction mode flyback pulse‐width modulation controller

Primary-side controlled flyback converter has been widely used in low-power and low-voltage products for its simple structure and low cost. As most applications require constant-current control, it is important for the integrated circuit to detect and express the output current accurately. This study proposes a novelty current detection and estimation circuit for primary-side controlled flyback controller. The circuit transmits the output current to voltage linearly with low power consumption and small layout area. Finally, a chip based on 0.6 μm complementary metal–oxide semiconductor process is fabricated using the current detection and estimation circuit in its constant-current loop to achieve constant output current.

High speed, open loop residue amplifier with linearity improvement

In this paper a new solution for a highly linear, high speed open loop (OL) residue amplifier for applications in high-speed pipelined analogue-digital converters is proposed. The proposed amplifier has a voltage gain of 4 (V/V) with <0.2% non-linearity error and 1.2 Vp-p output swing. The amplifier is compensated for process variations by using a novel gain control mechanism, thus maintains the linearity in all process conditions and also in the presence of a mismatch. The proposed amplifier is designed in 0.35 μm complementary metal-oxide semiconductor process, and the settling time is approximately 2 ns when driving two 1 pF single ended capacitive loads. It consumes 38 mW power from a 2.8 V supply and occupies 0.073 mm2 of die area. Simulations are performed in HSPICE using level 49 models.

A novel ±0.8 V high-performance voltage-tunable CDTA with enhanced bandwidth

In this article, we propose a novel high-performance complementary metal oxide semiconductor (CMOS) current differencing transconductance amplifier (CDTA) with a transconductance gain (GM) that can be linearly tuned by a voltage. By using a high-speed, low-voltage, cascaded current mirror active resistance compensation technique, the proposed CDTA circuit exhibits wide frequency bandwidths, high current tracking precisions as well as large output impedances. The linear-tunable GM of the CDTA is designed with the use of linear composite metal oxide semiconductor field-effect transistor as basic cells in the circuit. Combining these two approaches, several design concerns are studied, including: impedance characteristic, tracking errors, offset and linearity and noise. The prototype chip with a 0.25 mm2 area is fabricated in a GlobalFoundries’0.18 μm CMOS process. The simulated results and measured results with ±0.8 V DC supply voltages are presented, and show extremely wide bandwidths and wide linear tuning range. In addition, a fully differential band-pass filter for a high-speed system is also given as an example to confirm the high performance of the proposed circuit.

Output‐capacitorless segmented low‐dropout voltage regulator with controlled pass transistors

SummaryThis article presents a low quiescent current output‐capacitorless quasi‐digital complementary metal‐oxide‐semiconductor (CMOS) low‐dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade‐off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post‐simulated in HSPICE in a 0.18 µm CMOS process to supply a stable load current between 0 and 100 mA with a 40 pF on‐chip output capacitor, while consuming 4.8 μA quiescent current. The dropout voltage of the LDO is set to 200 mV for 1.8 V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively. Copyright © 2015 John Wiley &amp; Sons, Ltd.

Broadband complementary metal‐oxide semiconductor single‐pole‐double‐throw switch with improved power handling capability using dual‐gate metal‐oxide semiconductor field‐effect transistors

A broadband complementary metal-oxide semiconductor (CMOS) single-pole-double-throw (SPDT) switch based on a travelling-wave design with using dual-gate N-type metal-oxide semiconductor (NMOS) transistors is implemented in a 0.18 μm CMOS process for millimetre-wave applications. To further investigate the power handling capability in a dual-gate metal-oxide semiconductor field-effect transistor (MOSFET), this study analyses the mechanism of voltage swing distribution by using the proposed large-signal cascode model. Considering the parasitic gate-to-gate capacitance and the substrate effect, the simulations in this study can accurately predict the small-signal and power handling performances of the SPDT switch. The switch exhibits a measured 1 dB bandwidth of ∼51 GHz, ranging from 16 to 67 GHz with an insertion loss of 3.6 dB at 30 GHz. The measured isolation is also better than 22 dB. The measured power handling capability can achieve a 1 dB compression point at an input power of 23.8 dBm at 30 GHz with a negative body bias, and the simulation result shows a 1 dB compression point nearly 24 dBm. Based on the proposed model, the large-signal performances under different body biases can be significantly predicted when including the parasitic gate-to-gate capacitance in a dual-gate MOSFET.

A Capacitive Ammonia Sensor Using the Commercial 0.18 μm CMOS Process

The project presents an ammonia sensor with heater on-a-chip manufactured using the commercial 0.18 μm CMOS (complementary metal oxide semiconductor) process. The ammonia sensor is composed of a sensitive film, interdigital electrodes and a polysilicon heater. The sensor is a capacitive type and the sensitive film is ZrO2that is prepared by sol-gel method. The sensor requires a post-process to remove the sacrificial oxide layer and coat the ZrO2film on the interdigital electrodes. When the sensitive film absorbs ammonia vapor, the capacitance of the sensor generates a change. Experimental results show that the sensitivity of the ammonia sensor is 2.47 pF/ppm at 270 °C.