Mixed-mode Simulation Research Articles

Comparison of Logic Performance of CMOS Circuits Implemented With Junctionless and Inversion-Mode FinFETs

In this paper, we report the logic performance of CMOS circuits implemented with n- and p-channel junctionless (JL) FinFETs. A one-to-one comparison of the performance is made between such circuits and those implemented with n- and p-channel conventional inversion-mode (IM) FinFETs. The logic performance of a CMOS inverter is evaluated in terms of rise time and fall time for three different future technology nodes with the help of extensive 3-D device and mixed-mode circuit simulators. Frequency of oscillation of a three-stage ring oscillator (RO) is also obtained for such nodes. In spite of reduced ON-state current arising out of the higher channel doping and, hence, reduced carrier mobility in the JL devices, somewhat improved performance of the JL CMOS circuits over their IM counterparts are observed. For example, improvement of ~28% and ~10% in the rise time and fall time, respectively, for the inverter and ~12% in the frequency of oscillation of RO are observed for 10-nm technology node. Our investigations reveal reduced gate capacitance of the JL devices that in turn result in such improved performance of the JL CMOS circuits. Reduced gate capacitance also results in reduced dynamic power dissipation of JL CMOS circuits.

Analysis and Modeling of Cross-Coupling and Substrate Capacitances in GaN HEMTs for Power-Electronic Applications

In this paper, we present a capacitance model for field-plate AlGaN/GaN High Electron Mobility Transistor (HEMTs) accounting for the contribution of substrate capacitances and cross-coupling between field plates. TCAD simulations are performed to analyze both these contributions and analytical expressions for charges corresponding to the cross-coupling and substrate capacitances are presented in terms of our existing surface-potential-based model. The modeled results are validated by comparing the time-domain waveforms of a test circuit using a mixed-mode simulation setup in which the impact of cross-coupling and substrate capacitances on accuracy of switching transients predicted by the model is discussed.

High‐performance engineered gate transistor‐based compact digital circuits

A novel method for designing and realising compact digital circuits by engineering MOSFET gate electrode is proposed. The novelty is the use of gate engineered single devices in the pull-up (PU) and pull-down (PD) paths of a static CMOS gate instead of multiple transistors as used in conventional CMOS implementations of circuits. Herein, two input NAND, NOR, and exclusive-OR (XOR) gates employing the proposed gate engineering concept are designed and simulated. Engineered gate N-type MOS and P-type MOS are used for PD and pull-up circuits, respectively. Since only two devices are used for a complete circuit: one in PU network and other in PD network; therefore, area and power of the proposed circuits get reduced significantly in comparison with the conventional static CMOS circuits. Mixed mode simulations have shown that the proposed technique realises NAND, NOR and XOR operations perfectly and it can be extended to realise other combinational and sequential circuits easily.

Performance Enhancement of 22nm SRAM using Gate Engineered Multigate Independent FETs

Innovative device architectures are necessary to avail the advantages through scaling. One such Gate Engineered Multigate Independent FinFET (MIGFET) has been designed using 22nm technology and electrical characteristics such as drive current, leakage current, Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL) are found and compared with conventional Polysilicon gate material based device. Gate engineered devices are created with metals like Tungsten, Gold, Tantalum and Molybdenum. A 6-T SRAM cell is created using Mixed Mode Simulation in TCAD Sentaurus Software. It is found that gate engineered MIGFETs provides 35 to 55% performance enhancement than the polysilicon based FinFET.

Design and Simulation of Low-Power Logic Gates Based on Nanoscale Side-Contacted FED

A new nanoscale device has been already introduced as a side-contacted field effect diode (S-FED), which is composed of a diode and planar SOI-MOSFET. In this paper, S-FED is optimized in terms of work function, with due attention to the design of logic gates, such as NOT, NAND, NOR, and XOR. Results demonstrate that optimum work function is 4.7 eV in which the highest value of $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ can be achieved. Mixed-mode simulations are used to determine the performance of the proposed logic gates. Also, the proof regarding the mitigation of the total power consumption up to 56% is presented so that not gate based on S-FED improves power delay product by about 30%, compared with the CMOS-based version. A similar fabrication process with the CMOS technology could be asserted as the considerable advantage to pave the way of feasibly realizing the new generation of S-FED-based logic gates.

Charge-Steering Latch Design in 16 nm FinFET Technology for Improved Soft Error Hardness

A charge-steering based latch hardening technique with very low performance tradeoff and significant SEU hardness is presented. Mixed-mode 3D-TCAD simulations are used to illustrate the effect of charge steering in reducing the amount of collected charge at the critical sensitive nodes. Circuit simulations also highlight that the tradeoffs in terms of area, speed and power penalties are much lower compared to other hardening approaches, such as hysteresis and spatial-redundancy techniques. Alpha particle, heavy-ion, and proton test results for circuits designed in a 16 nm FinFET process indicate significant SEU hardness, comparable to DICE FF design, for low LET particles.

Single-Event Transient Response of Comparator Pre-Amplifiers in a Complementary SiGe Technology

The single-event transient (SET) response of the pre-amplification stage of two latched comparators designed using either npn or pnp silicon-germanium heterojunction bipolar transistors (SiGe HBTs) is investigated via two-photon absorption (TPA) carrier injection and mixed-mode TCAD simulations. Experimental data and TCAD simulations showed an improved SET response for the pnp comparator circuit. 2-D raster scans revealed that the devices in the pnp circuit exhibit a reduction in sensitive area of up to 80% compared to their npn counterparts. In addition, by sweeping the input voltage, the sensitive operating region with respect to SETs was determined. By establishing a figure-of-merit, relating the transient peaks and input voltage polarities, the pnp device was determined to have a 21.4% improved response with respect to input voltage. This study has shown that using pnp devices is an effective way to mitigate SETs, and could enable further radiation-hardening-by-design techniques.

Buffer Trap Related Knee Walkout and the Effects of Self-Heating in AlGaN/GaN HEMTs

Mixed-mode simulations of a class A amplifier is used to study the DC/RF dispersion commonly observed in AlGaN/GaN based HEMTs. We show that the observed knee walkout at frequencies greater than the emission rates of buffer traps (time constants tae > 1 week) is related to the steady state trap density and spatial location due to the DC operational bias. An increase in the drain bias point and an initial distortion of the RF signal, that is expected to disappear as the device global temperature reduces, is observed when a self-heating model is included. Finally, we propose that a reduction in the DC/RF dispersion is possible with a suitable location and concentration of an acceptor doping in the buffer.

Analysis of the reverse recovery oscillation of superjunction MOSFET body diode

The voltage and current oscillations occasionally occur during the reverse recovery transient of the superjunction MOSFET body diode. This paper identifies the unique reverse recovery oscillation characteristics of the superjunction MOSFET body diode. Base on the experimental investigation and theoretical analysis, the various reverse recovery oscillation mechanisms are clarified. At first, with a discrete 650V/47A superjunction MOSFET utilized, the high-frequency and low-frequency oscillation characteristics during the reverse recovery transient are obtained by the double-pulse test. After the theoretical analysis, it is found that the superjunction MOSFET body diode has various oscillation mechanisms depending on its drift region injection level. Under high-level injection condition, the high-frequency oscillation occurs due to the plasma extraction transient-time (PETT) effect. Under low-level injection condition, the body diode’s snappy reverse recovery results in the low-frequency LC oscillation. In the end of the paper, the oscillation behaviors under both high and low level injection conditions are reproduced by the mixed-mode numerical simulation, the simulation results validate the proposed oscillation mechanisms.

Analysis of the dynamic avalanche of carrier stored trench bipolar transistor (CSTBT) during clamped inductive turn-off transient

The dynamic avalanche has a huge impact on the switching robustness of carrier stored trench bipolar transistor (CSTBT). The purpose of this work is to investigate the CSTBT’s dynamic avalanche mechanism during clamped inductive turn-off transient. At first, with a Mitsubishi 600V/150A CSTBT and a Infineon 600V/200A field stop insulated gate bipolar transistor (FS-IGBT) utilized, the clamped inductive turn-off characteristics are obtained by double pulse test. The unclamped inductive switching (UIS) test is also utilized to identify the CSTBT’s clamping voltage under dynamic avalanche condition. After the test data analysis, it is found that the CSTBT’s dynamic avalanche is abnormal and can be triggered under much looser condition than the conventional buffer layer IGBT. The comparison between the FS-IGBT and CSTBT’s experimental results implies that the CSTBT’s abnormal dynamic avalanche phenomenon may be induced by the carrier storage (CS) layer. Based on the semiconductor physics, the electric field distribution and dynamic avalanche generation in the depletion region are analyzed. The analysis confirms that the CS layer is the root cause of the CSTBT’s abnormal dynamic avalanche mechanism. Moreover, the CSTBT’s negative gate capacitance effect is also investigated to clarify the underlying mechanism of the gate voltage bump observed in the test. In the end, the mixed-mode numerical simulation is utilized to reproduce the CSTBT’s dynamic avalanche behavior. The simulation results validate the proposed dynamic avalanche mechanisms.

Using Mixed-Signal Defect Simulation to Close the Loop Between Design and Test

By the time volume production test statistics are known, it is usually uneconomical to significantly modify a mixed-signal design to improve test cost or coverage, or to add redundancy to improve yield or reliability. Fault simulation could provide immediate feedback to designers about the impact of design on test time, test cost, and test coverage of manufacturing defects, but simulating all potential defects in a mixed-signal circuit is usually not practical. This paper first summarizes previous fault simulators and likelihood-weighted random sampling theory. It then describes a defect simulator developed for industrial mixed-signal circuits. The mixed-mode simulator simulates realistic random defectivity, and reports likelihood-weighted defect coverage based on user-provided likelihoods for opens, shorts, and excessive variations, and for user-defined defects. A variety of techniques is described that reduces total defect simulation time. We provide two small circuit examples to illustrate how test coverage was measured for circuits in pre-production ICs. An additional benefit of defect simulation is measurement of a circuit’s defect tolerance, whether the tolerance is added to improve reliability or yield.

Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology

The device and circuit performance of a 20-nm gate length InGaAs and Ge hybrid CMOS based on an implant free quantum well (QW) device architecture is studied using a multiscale approach combining ensemble Monte Carlo simulation, drift-diffusion simulation, compact modeling, and TCAD mixed-mode circuit simulation. We have found that the QW and doped substrate, used in the hybrid CMOS, help to reduce short-channel effects by enhancing carrier confinement. The QW also reduces the destructive impact of a low density of states in III–V materials. In addition, the calculated access resistance is found to be a much lower than in Si counterparts thanks to a heavily doped overgrowth source/drain contact. We predict an overall low gate capacitance and a large drive current when compared with Si-CMOS that leads to a significant reduction in a circuit propagation time delay ( ${\sim }5.5$ ps).

Statistical Variability Analysis of SRAM Cell for Emerging Transistor Technologies

Several emerging devices have been proposed to continue the CMOS scaling. To assess scalability, device and circuit variability estimation is essential. Variability in static noise margin (SNM) in a 6T-SRAM cell is a key metric to assess the impact of device-level variability at the circuit level. This is usually enabled by SPICE simulations, which needs device compact models. However, the development of a SPICE model usually takes a significant amount of time (e.g., a few years). In this paper, we present a method to enable the evaluation of the SRAM cell SNM variability based on the $I_{D}$ – $V_{G}$ distribution at various $V_{\mathrm{ DS}}$ values of a device (obtained either experimentally or from TCAD), which can enable this assessment before the development of a SPICE model. Thus, it enhances the accuracy by being able to capture the effects of full $I_{D}$ – $V_{G}$ distribution rather than just $V_{T}$ distribution. The method is validated against HSPICE for a variety of SRAM parameters, such as Read, Hold, and Write SNM, write trip point, and read current ( $I_{\mathrm{ READ}}$ ) to show excellent accuracy. The method also shows a $30\times $ improvement in computational efficiency over mixed-mode TCAD-based stochastic SRAM simulation. A case study for the comparison of recently proposed low-variability EDFinFET with FinFET is presented using this method.

A Highly Reliable Memory Cell Design Combined With Layout-Level Approach to Tolerant Single-Event Upsets

In this paper, a highly reliable radiation hardened by design memory cell (RHD12) using 12 transistors in a 65-nm CMOS commercial technology is proposed. Combining with layout-level design, the TCAD mixed-mode simulation results indicate that the RHD12 not only can fully tolerant the single-event upset occurring on any one of its single nodes but can also tolerant single-event multiple-node upsets in a single memory cell, which are caused by charge sharing. Moreover, a set of HSPICE post-simulations are done to evaluate the RHD12 and other state-of-the-art memory cells, which show that our proposed memory cell has better performance, considering the area, power consumption, and access time.

Mixed-mode simulation and analysis of 3D double gate junctionless nanowire transistor for CMOS circuit applications

Circuit performance of an ultra-thin 3D double gate junctionless nanowire transistor, with an emphasis on digital applications, is investigated. Extensive analysis of inverter circuit and universal gates are performed using mixed mode simulation to understand the characteristics and circuit performance of the device. Different properties, like voltage transfer characteristics, transient response, DC gain, and noise margin of these circuits is studied. Furthermore, to explore the influence of high-K gate dielectrics, we examined circuit performance of the junctionless nanowire device with different gate dielectrics (SiO2, Si3N4, and HfO2). Results show that the devices with high-K gate dielectric (HfO2) have improved circuit performance.

Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology

This paper describes the stochastic-based Spin-Programmable Gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in field programmable gate arrays (FPGAs), our study, for the first time, attempts to use the quantum-induced stochastic property exhibited by spintronic devices directly for reconfiguration and logic computation. Specifically, the SPGA was designed from scratch for high performance, routability, and ease-of-use. It supports variable-granularity multiple-input-multiple-output (MIMO) logic blocks and variable-length bypassing interconnects with a symmetrical structure. Due to its unconventional architectural features, the SPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new technology mapping algorithm based on computing (k, l)-cut, a new placement algorithm, and a modified delay-based routing procedure.Previous studies have shown that, simply replacing reconfiguration memory bits with spintronic devices, the conventional 2D island-style FPGA architecture can achieve approximately 5 times area savings, 2 times speedup and 1.6 times power savings. Our mixed-mode simulation results have shown that, with FPGA architecture innovations, on average, a SPGA can further achieve more than 10 times improvement in logic density, about 5 times improvement in average net delay, and about 5 times improvement in the critical-path delay for the largest 12 MCNC benchmark circuits over an island-style baseline FPGA with spintronic configuration bits.

Line-impedance matching and signal conditioning capabilities for high-speed feed-forward voltage-mode transmit drivers

This work presents the design and implementation of a power-efficient 2-tap feed-forward voltage mode driver which has impedance tuning and signal conditioning capabilities. The driver has a robust mechanism to match its impedance to the line impedance even when signal conditioning is enabled which minimizes reflection and improves signal quality. A mixed signal approach that detects and compensates for NMOS and PMOS transistor resistance variation is presented. An analog circuit detects the driver's resistance variation, and a digital circuit controls an analog compensation circuit to maintain line impedance matching for all signal conditioning configurations of the driver. When maximum signal conditioning is enabled, the driver can transmit a 40Gbits/sec PRBS7 signal through a 10 in. FR4 channel. It achieves a differential eye-opening amplitude of 100mVppd and an eye-opening width of 0.8UI consuming 9.7mW of at-speed power. Simulations demonstrate that worst case impedance deviation from 50Ω due to process, voltage and temperature variation is 2.7%. The driver is designed in 28nm CMOS process using a 0.85V nominal supply voltage. It is simulated using HSPICE circuit simulator and mixed mode simulations tools.

Numerical Simulation and Analysis of the Switching Performance for Printable Low-Voltage Organic Thin-Film Transistors in Active-Matrix Backplanes

To achieve low-voltage organic thin-film transistors (OTFTs) with printing or coating processes over large area, a thick gate dielectric layer is preferred. Taking this into consideration, a common solution for low-voltage OTFTs is using large-permittivity (high- $k$ ) dielectric material to enlarge the gate dielectric capacitance. Our recent work shows that reducing the subgap density of states (DOS) at the channel can also help to achieve low-voltage OTFTs. This approach does not need large gate dielectric capacitance, and thus a low- $k$ and thick gate dielectric layer can be used. In this work, device/circuit mixed-mode simulations are carried out to compare the performance of the two type low-voltage OTFTs as switches in active-matrix backplanes. It is shown that the low-voltage OTFT with reduced subgap DOS can achieve faster charging and discharging. The less parasitic and storage capacitance with the low- $k$ dielectric layer would also reduce the required dynamic power.

Impact of Random Variations on Cell Stability and Write-Ability of Low-Voltage SRAMs Using Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) MOSFETs

This letter evaluates and analyzes the impacts of random variations on cell stability and write-ability of low-voltage SRAMs using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) node with the aid of atomistic TCAD mixed-mode simulations. Our study indicates that, for 6T SRAM, the monolayer/bilayer TMD devices may fail to provide the $6\sigma $ yield requirement for read static noise margin (RSNM) due to severe metal-gate work function variation in spite of their excellent electrostatics, and hence circuit techniques, such as bootstrapped dynamic power rails or the standard 8T cell, are needed. Besides, $R_{\mathrm {SD}}$ as a major concern of TMDs should be less of an issue for near-/sub-threshold SRAMs for ultra low-power applications. For the standard 8T cell structure, the RSNMs of both monolayer and bilayer 8T SRAMs improve significantly, and the bilayer 8T SRAM exhibits better write static noise margin (WSNM). In addition, write-assist techniques (including negative bit-line, boosted word-line, and lower cell supply) for improving WSNM are examined and shown to be more effective for monolayer 8T SRAMs than the bilayer counterparts.

Design and simulation of high-performance lateral bipolar junction transistor on partial buried oxide

ABSTRACTIn this work, we propose a new structure of a lateral bipolar junction transistor (LAT-BJT) on partial buried oxide (PBOX). The novelty of the proposed LAT-BJT device is the use of PBOX, covering just base and emitter regions only. A two-dimensional (2D) calibrated simulation study of the proposed LAT-BJT device has shown that the proposed LAT-BJT on PBOX’s performance is unique when the PBOX is just covering base and emitter regions. At this length of PBOX, a sharp enhancement in cut-off frequency (fT) (~10 times higher) is achieved in the proposed LAT-BJT on PBOX in comparison to an LAT-BJT on silicon-on-insulator (SOI). The breakdown voltage of the proposed LAT-BJT on PBOX is double than that of the LAT-BJT on SOI device at this PBOX length. A notable enhancement in current gain (β) is observed in the proposed LAT-BJT on PBOX in comparison to the LAT-BJT on bulk device. To check the performance of the proposed LAT-BJT on PBOX at the circuit level, two inverters have been designed and simulated using the mixed-mode simulations of Atlas simulator. It has been observed that the proposed LAT-BJT on PBOX significantly outperforms the conventional LAT-BJT device in switching performance. A notable improvement of 32% in ON delay and 72.9% in OFF delay is obtained in the proposed LAT-BJT on PBOX device in comparison to the conventional LAT-BJT device.