Analysis of the dynamic avalanche of carrier stored trench bipolar transistor (CSTBT) during clamped inductive turn-off transient

Abstract

The dynamic avalanche has a huge impact on the switching robustness of carrier stored trench bipolar transistor (CSTBT). The purpose of this work is to investigate the CSTBT’s dynamic avalanche mechanism during clamped inductive turn-off transient. At first, with a Mitsubishi 600V/150A CSTBT and a Infineon 600V/200A field stop insulated gate bipolar transistor (FS-IGBT) utilized, the clamped inductive turn-off characteristics are obtained by double pulse test. The unclamped inductive switching (UIS) test is also utilized to identify the CSTBT’s clamping voltage under dynamic avalanche condition. After the test data analysis, it is found that the CSTBT’s dynamic avalanche is abnormal and can be triggered under much looser condition than the conventional buffer layer IGBT. The comparison between the FS-IGBT and CSTBT’s experimental results implies that the CSTBT’s abnormal dynamic avalanche phenomenon may be induced by the carrier storage (CS) layer. Based on the semiconductor physics, the electric field distribution and dynamic avalanche generation in the depletion region are analyzed. The analysis confirms that the CS layer is the root cause of the CSTBT’s abnormal dynamic avalanche mechanism. Moreover, the CSTBT’s negative gate capacitance effect is also investigated to clarify the underlying mechanism of the gate voltage bump observed in the test. In the end, the mixed-mode numerical simulation is utilized to reproduce the CSTBT’s dynamic avalanche behavior. The simulation results validate the proposed dynamic avalanche mechanisms.