A process optimization method for carrier stored trench bipolar transistor (CSTBT) device

Abstract

This paper presents a process optimization method for the carrier stored trench bipolar transistor (CSTBT) device demonstrated by TCAD numerical simulations. By adjusting the injection sequence of carrier stored (CS) layer, the injection efficiency of the CS layer has been significantly improved, and the trade-off of on-state voltage drop (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> ) and collector saturation current (IC <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</inf> ) has been almost fully optimized. TCAD simulation results show that the IC <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</inf> and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> of the CSTBT with optimized process are reduced by 19.7% and 15.1%, respectively. Additionally, comparing the CSTBT with the same Von under the two processes, the IC <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</inf> and turn-off time of the CSTBT with optimized process are reduced by 76.1% and 7.8%, respectively. Besides, after the process optimization, the gate trench depth of the device can be further reduced. Result shows shallower gate trench can offer larger design freedom for obtaining excellent trade-off relationship between turn-off loss (E <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> ) and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> . Therefore, this process optimization method is an attractive solution for power electronics applications.