High Performance Carrier Stored Trench Bipolar Transistor with Shield Emitter Trench

Abstract

A novel high performance carrier stored trench bipolar transistor with shield emitter trench (SET-CSTBT) is proposed. The proposed SET-CSTBT features a shallow gate trench (SGT) shielded by a deep emitter trench with a thick oxide layer. The SGT reduces the gate depth and the deep SET with thick oxide layer shields the negative impact of the CS layer and SGT on the breakdown voltage $(BV)$ . Simulation results show that the on-state voltage drop $(V_{\mathrm{ceon}})$ at, $J_{\mathrm{ce}}=150\mathrm{A}/\mathrm{cm}^{2}$ for the proposed SET-CSTBT is 1.23V compare to that of 1.30V for the conventional CSTBT (Con-CSTBT) with same $BV$ . Meanwhile, the gate-collector capacitance $(C_{\mathrm{gc}})$ at $V_{\mathrm{ce}}=20\mathrm{V}$ for the proposed SET-CSTBT is reduced by 76.5% compared to that of the Con-CSTBT. As a result, the trade-off relationship between the $V_{\mathrm{ceon}}$ and turn-off loss $(E_{\mathrm{off}})$ is significantly improved. With the same $V_{\mathrm{ceon}}$ of 1.30V, the $E_{\mathrm{off}}$ is reduced from 19.12mJ/cm2 of the Con-CSTBT to 8.97mJ/cm2 of the proposed SET-CSTBT.