A high performance carrier stored trench bipolar transistor with a field-modified P-base region

Abstract

A novel high performance carrier stored trench bipolar transistor (CSTBT) with a field- modified P-base region is proposed. Due to the p-pillars inserted into the drift region extending the P-base region to the bottom of the trench gate, the electric field around the trench gate is modified, preventing the CSTBT from breakdown in advance caused by a concentration of the electric field at the edge of the trench gate. The p-pillars under the p-well forming the novel P-base region also provide extra paths for hole transportation. Thus, the switching time is also reduced. Simulation results have shown that the blocking voltage (BV) of the novel CSTBT is almost 430 V higher exhibiting avalanche breakdown properties compared with the conventional CSTBT. Moreover, the turn-off time of the novel structure is 0.3 μs (17%) shorter than the conventional CSTBT with the same gate length.