Mixed-mode simulation and analysis of 3D double gate junctionless nanowire transistor for CMOS circuit applications

Abstract

Circuit performance of an ultra-thin 3D double gate junctionless nanowire transistor, with an emphasis on digital applications, is investigated. Extensive analysis of inverter circuit and universal gates are performed using mixed mode simulation to understand the characteristics and circuit performance of the device. Different properties, like voltage transfer characteristics, transient response, DC gain, and noise margin of these circuits is studied. Furthermore, to explore the influence of high-K gate dielectrics, we examined circuit performance of the junctionless nanowire device with different gate dielectrics (SiO2, Si3N4, and HfO2). Results show that the devices with high-K gate dielectric (HfO2) have improved circuit performance.